)]}'
{
  "commit": "a3ea30af9f485e0561cdb91221ea1663cba82813",
  "tree": "94ae4a8c5221f8a91272a12cb44d22cf60b6d82b",
  "parents": [
    "abf10296ea7fcb250a6cfae307df39903ddad21d"
  ],
  "author": {
    "name": "Domenic Nutile",
    "email": "domenic.nutile@gmail.com",
    "time": "Tue Sep 29 14:34:15 2026 -0400"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Tue Sep 29 14:34:15 2026 -0400"
  },
  "message": "[AMDGPU] Don\u0027t spill an SGPR while SCC is live in frame index lowering (#224080)\n\nWhen SCC is live into a scalar frame index user, the scaling path avoids\nSALU ops that write SCC by computing the address in a VGPR and reading\nit\nback with V_READFIRSTLANE_B32. If the destination of that readfirstlane\nis\nscavenged with spilling allowed, an AMDGPU SGPR spill writes inactive\nlanes, so it flips EXEC with S_NOT_B64 and clobbers SCC. Instead,\nscavenge\nthat register with AllowSpill\u003dfalse.\n\n---\n\n\u003csub\u003eStack created with \u003ca\nhref\u003d\"https://github.com/github/gh-stack\"\u003eGitHub Stacks CLI\u003c/a\u003e • \u003ca\nhref\u003d\"https://gh.io/stacks-feedback\"\u003eGive Feedback 💬\u003c/a\u003e\u003c/sub\u003e",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "1aa423e1da647d2b35a108494e356b778f35e066",
      "old_mode": 33188,
      "old_path": "llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp",
      "new_id": "ced26286954512eb5628faf06073a2a9ca748fb4",
      "new_mode": 33188,
      "new_path": "llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp"
    },
    {
      "type": "modify",
      "old_id": "d9e1a0fcaf3a76edf84084e1f9f7bf82283cb8c8",
      "old_mode": 33188,
      "old_path": "llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir",
      "new_id": "c499f00a573618d96d3c9a3a75d94e02a966c129",
      "new_mode": 33188,
      "new_path": "llvm/test/CodeGen/AMDGPU/sgpr-spill-to-vmem-scc-clobber-reserved-exec-copy.mir"
    }
  ]
}