llvm/test/CodeGen/AMDGPU/si-pre-allocate-wwm-regs.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -run-pass=si-pre-allocate-wwm-regs -o - %s  | FileCheck %s
# RUN: llc -mtriple=amdgcn -mcpu=tahiti -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -run-pass=si-pre-allocate-wwm-regs -o - %s | FileCheck %s --check-prefix=CHECK2

# RUN: llc -mtriple=amdgcn -passes=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s  | FileCheck %s
# RUN: llc -mtriple=amdgcn -verify-machineinstrs -amdgpu-prealloc-sgpr-spill-vgprs -passes=si-pre-allocate-wwm-regs -o - -mcpu=tahiti %s | FileCheck %s --check-prefix=CHECK2

# COM: auto-generated updates might remove checks for MachineFunctionInfo reserved registers.

---

name: pre_allocate_wwm_regs_strict
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr1
    ; CHECK-LABEL: name: pre_allocate_wwm_regs_strict
    ; CHECK: wwmReservedRegs:
    ; CHECK-NEXT: - '$vgpr0'
    ; CHECK: liveins: $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
    ; CHECK-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
    ; CHECK-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    ; CHECK-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0, implicit $exec
    ; CHECK-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
    ;
    ; CHECK2-LABEL: name: pre_allocate_wwm_regs_strict
    ; CHECK2: liveins: $sgpr1
    ; CHECK2-NEXT: {{  $}}
    ; CHECK2-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
    ; CHECK2-NEXT: renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
    ; CHECK2-NEXT: $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    ; CHECK2-NEXT: dead $vgpr0 = V_MOV_B32_dpp $vgpr0, [[DEF]], 323, 12, 15, 0, implicit $exec
    ; CHECK2-NEXT: $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
    ; CHECK2-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
    %0:vgpr_32 = IMPLICIT_DEF
    renamable $sgpr4_sgpr5 = ENTER_STRICT_WWM -1, implicit-def $exec, implicit-def $scc, implicit $exec
    %1:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
    %2:vgpr_32 = V_MOV_B32_dpp %1, %0, 323, 12, 15, 0, implicit $exec
    $exec = EXIT_STRICT_WWM killed renamable $sgpr4_sgpr5
    %3:vgpr_32 = COPY %0
...
---

name: pre_allocate_wwm_spill_to_vgpr
tracksRegLiveness: true
body: |
  bb.0:
    liveins: $sgpr1
    ; CHECK-LABEL: name: pre_allocate_wwm_spill_to_vgpr
    ; CHECK: liveins: $sgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
    ; CHECK-NEXT: dead [[SI_SPILL_S32_TO_VGPR:%[0-9]+]]:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
    ; CHECK-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
    ;
    ; CHECK2-LABEL: name: pre_allocate_wwm_spill_to_vgpr
    ; CHECK2: wwmReservedRegs:
    ; CHECK2-NEXT: - '$vgpr0'
    ; CHECK2: liveins: $sgpr1
    ; CHECK2-NEXT: {{  $}}
    ; CHECK2-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
    ; CHECK2-NEXT: dead $vgpr0 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, [[DEF]]
    ; CHECK2-NEXT: dead [[COPY:%[0-9]+]]:vgpr_32 = COPY [[DEF]]
    %0:vgpr_32 = IMPLICIT_DEF
    %1:vgpr_32 = SI_SPILL_S32_TO_VGPR $sgpr1, 0, %0
    %2:vgpr_32 = COPY %0
...