llvm/test/CodeGen/AMDGPU/shrink-instructions-implicit-vcclo.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=si-shrink-instructions --verify-machineinstrs %s -o - | FileCheck -check-prefix=GCN %s

# Make sure the implicit vcc_lo of V_CNDMASK is preserved and not promoted to vcc.
---

name:            shrink_cndmask_implicit_vcc_lo
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1
    ; GCN-LABEL: name: shrink_cndmask_implicit_vcc_lo
    ; GCN: liveins: $vgpr0, $vgpr1
    ; GCN-NEXT: {{  $}}
    ; GCN-NEXT: $vgpr0 = COPY $vgpr0
    ; GCN-NEXT: $vgpr1 = COPY $vgpr0
    ; GCN-NEXT: V_CMP_LT_I32_e32 0, $vgpr0, implicit-def $vcc_lo, implicit $exec, implicit-def $vcc
    ; GCN-NEXT: $vgpr2 = V_CNDMASK_B32_e32 0, $vgpr1, implicit $vcc_lo, implicit $exec
    ; GCN-NEXT: S_NOP 0
    $vgpr0 = COPY $vgpr0
    $vgpr1 = COPY $vgpr0
    V_CMP_LT_I32_e32 0, $vgpr0, implicit-def $vcc_lo, implicit $exec, implicit-def $vcc
    $vgpr2 = V_CNDMASK_B32_e64 0, 0, 0, $vgpr1, $vcc_lo, implicit $exec
    S_NOP 0

...