| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX10 -enable-var-scope %s |
| ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1030 -verify-machineinstrs -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX10 %s |
| ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11 -enable-var-scope %s |
| ; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx1100 -verify-machineinstrs -global-isel -global-isel-abort=2 < %s | FileCheck -check-prefixes=GFX11 %s |
| ; Test codegen with readfirstlane used by M0. |
| ; |
| ; M0 can only be written to by SALU instructions so we can't emit |
| ; a v_readfirstlane_b32 m0 |
| |
| define void @test_readfirstlane_m0(i32 %arg) { |
| ; GFX10-LABEL: test_readfirstlane_m0: |
| ; GFX10: ; %bb.0: |
| ; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX10-NEXT: v_readfirstlane_b32 s4, v0 |
| ; GFX10-NEXT: s_mov_b32 m0, s4 |
| ; GFX10-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) |
| ; GFX10-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX10-NEXT: s_setpc_b64 s[30:31] |
| ; |
| ; GFX11-LABEL: test_readfirstlane_m0: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) |
| ; GFX11-NEXT: v_readfirstlane_b32 s0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-NEXT: s_mov_b32 m0, s0 |
| ; GFX11-NEXT: s_sendmsg sendmsg(MSG_INTERRUPT) |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: s_setpc_b64 s[30:31] |
| %1 = call i32 @llvm.amdgcn.readfirstlane.i32(i32 %arg) |
| call void @llvm.amdgcn.s.sendmsg(i32 1, i32 %1) |
| ret void |
| } |
