llvm/test/CodeGen/AMDGPU/insert-skips-ignored-insts.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass si-pre-emit-peephole %s -o - | FileCheck %s

---

name: no_count_dbg_value
body: |
  ; CHECK-LABEL: name: no_count_dbg_value
  ; CHECK: bb.0:
  ; CHECK-NEXT:   successors: %bb.1(0x40000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr1 = V_MOV_B32_e32 7, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.1:
  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 0, implicit $exec
  ; CHECK-NEXT:   DBG_VALUE
  ; CHECK-NEXT:   DBG_VALUE
  ; CHECK-NEXT:   DBG_VALUE
  ; CHECK-NEXT:   DBG_VALUE
  ; CHECK-NEXT:   DBG_VALUE
  ; CHECK-NEXT:   DBG_VALUE
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.2:
  ; CHECK-NEXT:   successors: %bb.3(0x80000000)
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT:   $vgpr0 = V_MOV_B32_e32 1, implicit $exec
  ; CHECK-NEXT: {{  $}}
  ; CHECK-NEXT: bb.3:
  ; CHECK-NEXT:   S_ENDPGM 0
  bb.0:
    successors: %bb.1, %bb.2

    $vgpr1 = V_MOV_B32_e32 7, implicit $exec
    S_CBRANCH_EXECZ %bb.2, implicit $exec

  bb.1:
    successors: %bb.2
    $vgpr0 = V_MOV_B32_e32 0, implicit $exec
    DBG_VALUE
    DBG_VALUE
    DBG_VALUE
    DBG_VALUE
    DBG_VALUE
    DBG_VALUE

  bb.2:
    $vgpr0 = V_MOV_B32_e32 1, implicit $exec

  bb.3:
    S_ENDPGM 0
...