| ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 |
| ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=kaveri -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,CI %s |
| ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=tonga -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=CIVI,GFX8 %s |
| ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx900 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX9 %s |
| ; RUN: llc -amdgpu-scalarize-global-loads=false -mcpu=gfx1100 -mtriple=amdgcn--amdhsa -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GFX11 %s |
| |
| ; FIXME: Should be able to do scalar op |
| define amdgpu_kernel void @s_fneg_f16(ptr addrspace(1) %out, half %in) #0 { |
| ; CI-LABEL: s_fneg_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[8:9], 0x2 |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: flat_store_short v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: s_fneg_f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX8-NEXT: flat_store_short v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: s_fneg_f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: global_store_short v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: s_fneg_f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_clause 0x1 |
| ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8 |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 |
| ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %fneg = fsub half -0.0, %in |
| store half %fneg, ptr addrspace(1) %out |
| ret void |
| } |
| |
| ; FIXME: Should be able to use bit operations when illegal type as |
| ; well. |
| define amdgpu_kernel void @v_fneg_f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { |
| ; CI-LABEL: v_fneg_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 1, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 |
| ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; CI-NEXT: flat_load_ushort v2, v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: v_xor_b32_e32 v2, 0x8000, v2 |
| ; CI-NEXT: flat_store_short v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: v_fneg_f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8 |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 1, v0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX8-NEXT: flat_load_ushort v2, v[0:1] |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: v_xor_b32_e32 v2, 0x8000, v2 |
| ; GFX8-NEXT: flat_store_short v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: v_fneg_f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 1, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_load_ushort v1, v0, s[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: v_xor_b32_e32 v1, 0x8000, v1 |
| ; GFX9-NEXT: global_store_short v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: v_fneg_f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 1, v0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_load_u16 v1, v0, s[0:1] |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) |
| ; GFX11-NEXT: v_xor_b32_e32 v1, 0x8000, v1 |
| ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %tid = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.in = getelementptr inbounds half, ptr addrspace(1) %in, i32 %tid |
| %gep.out = getelementptr inbounds half, ptr addrspace(1) %in, i32 %tid |
| %val = load half, ptr addrspace(1) %gep.in, align 2 |
| %fneg = fsub half -0.0, %val |
| store half %fneg, ptr addrspace(1) %gep.out |
| ret void |
| } |
| |
| define amdgpu_kernel void @s_fneg_free_f16(ptr addrspace(1) %out, i16 %in) #0 { |
| ; CI-LABEL: s_fneg_free_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[8:9], 0x2 |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: flat_store_short v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: s_fneg_free_f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX8-NEXT: flat_store_short v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: s_fneg_free_f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: global_store_short v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: s_fneg_free_f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_clause 0x1 |
| ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8 |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: s_xor_b32 s2, s2, 0x8000 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 |
| ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %bc = bitcast i16 %in to half |
| %fsub = fsub half -0.0, %bc |
| store half %fsub, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_fneg_fold_f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { |
| ; CI-LABEL: v_fneg_fold_f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: flat_load_ushort v0, v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e64 v0, -v0 |
| ; CI-NEXT: v_mul_f32_e32 v0, v0, v1 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v2, v0 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: flat_store_short v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: v_fneg_fold_f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s2 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s3 |
| ; GFX8-NEXT: flat_load_ushort v2, v[0:1] |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: v_mul_f16_e64 v2, -v2, v2 |
| ; GFX8-NEXT: flat_store_short v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: v_fneg_fold_f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_load_ushort v1, v0, s[2:3] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: v_mul_f16_e64 v1, -v1, v1 |
| ; GFX9-NEXT: global_store_short v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: v_fneg_fold_f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_load_u16 v1, v0, s[2:3] |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) |
| ; GFX11-NEXT: v_mul_f16_e64 v1, -v1, v1 |
| ; GFX11-NEXT: global_store_b16 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %val = load half, ptr addrspace(1) %in |
| %fsub = fsub half -0.0, %val |
| %fmul = fmul half %fsub, %val |
| store half %fmul, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @s_fneg_v2f16(ptr addrspace(1) %out, <2 x half> %in) #0 { |
| ; CI-LABEL: s_fneg_v2f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[8:9], 0x2 |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: flat_store_dword v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: s_fneg_v2f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX8-NEXT: flat_store_dword v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: s_fneg_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: s_fneg_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_clause 0x1 |
| ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8 |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 |
| ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in |
| store <2 x half> %fneg, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @s_fneg_v2f16_nonload(ptr addrspace(1) %out) #0 { |
| ; CIVI-LABEL: s_fneg_v2f16_nonload: |
| ; CIVI: ; %bb.0: |
| ; CIVI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CIVI-NEXT: ;;#ASMSTART |
| ; CIVI-NEXT: ; def s2 |
| ; CIVI-NEXT: ;;#ASMEND |
| ; CIVI-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; CIVI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CIVI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CIVI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CIVI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CIVI-NEXT: flat_store_dword v[0:1], v2 |
| ; CIVI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: s_fneg_v2f16_nonload: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: ;;#ASMSTART |
| ; GFX9-NEXT: ; def s2 |
| ; GFX9-NEXT: ;;#ASMEND |
| ; GFX9-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: s_fneg_v2f16_nonload: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: ;;#ASMSTART |
| ; GFX11-NEXT: ; def s2 |
| ; GFX11-NEXT: ;;#ASMEND |
| ; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %in = call i32 asm sideeffect "; def $0", "=s"() |
| %in.bc = bitcast i32 %in to <2 x half> |
| %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in.bc |
| store <2 x half> %fneg, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_fneg_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { |
| ; CI-LABEL: v_fneg_v2f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x2 |
| ; CI-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_add_i32_e32 v0, vcc, s0, v0 |
| ; CI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; CI-NEXT: flat_load_dword v2, v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 |
| ; CI-NEXT: flat_store_dword v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: v_fneg_v2f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8 |
| ; GFX8-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: v_add_u32_e32 v0, vcc, s0, v0 |
| ; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc |
| ; GFX8-NEXT: flat_load_dword v2, v[0:1] |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: v_xor_b32_e32 v2, 0x80008000, v2 |
| ; GFX8-NEXT: flat_store_dword v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: v_fneg_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x8 |
| ; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_load_dword v1, v0, s[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: v_fneg_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x8 |
| ; GFX11-NEXT: v_and_b32_e32 v0, 0x3ff, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) |
| ; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_load_b32 v1, v0, s[0:1] |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) |
| ; GFX11-NEXT: v_xor_b32_e32 v1, 0x80008000, v1 |
| ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %tid = call i32 @llvm.amdgcn.workitem.id.x() |
| %gep.in = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid |
| %gep.out = getelementptr inbounds <2 x half>, ptr addrspace(1) %in, i32 %tid |
| %val = load <2 x half>, ptr addrspace(1) %gep.in, align 2 |
| %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val |
| store <2 x half> %fneg, ptr addrspace(1) %gep.out |
| ret void |
| } |
| |
| define amdgpu_kernel void @fneg_free_v2f16(ptr addrspace(1) %out, i32 %in) #0 { |
| ; CI-LABEL: fneg_free_v2f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dword s2, s[8:9], 0x2 |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_mov_b32_e32 v2, s2 |
| ; CI-NEXT: flat_store_dword v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: fneg_free_v2f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: v_mov_b32_e32 v2, s2 |
| ; GFX8-NEXT: flat_store_dword v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: fneg_free_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dword s2, s[8:9], 0x8 |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, s2 |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: fneg_free_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_clause 0x1 |
| ; GFX11-NEXT: s_load_b32 s2, s[4:5], 0x8 |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: s_xor_b32 s2, s2, 0x80008000 |
| ; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) |
| ; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2 |
| ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %bc = bitcast i32 %in to <2 x half> |
| %fsub = fsub <2 x half> <half -0.0, half -0.0>, %bc |
| store <2 x half> %fsub, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_fneg_fold_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 { |
| ; CI-LABEL: v_fneg_fold_v2f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s2 |
| ; CI-NEXT: v_mov_b32_e32 v1, s3 |
| ; CI-NEXT: flat_load_dword v0, v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: v_xor_b32_e32 v2, 0x80008000, v0 |
| ; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; CI-NEXT: v_lshrrev_b32_e32 v3, 16, v2 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v3, v3 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v2, v2 |
| ; CI-NEXT: v_mul_f32_e32 v1, v3, v1 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v3, v1 |
| ; CI-NEXT: v_mul_f32_e32 v0, v2, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v2, v0 |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_lshlrev_b32_e32 v3, 16, v3 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; CI-NEXT: flat_store_dword v[0:1], v2 |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: v_fneg_fold_v2f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s2 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s3 |
| ; GFX8-NEXT: flat_load_dword v2, v[0:1] |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: v_mul_f16_sdwa v3, -v2, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1 |
| ; GFX8-NEXT: v_mul_f16_e64 v2, -v2, v2 |
| ; GFX8-NEXT: v_or_b32_e32 v2, v2, v3 |
| ; GFX8-NEXT: flat_store_dword v[0:1], v2 |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: v_fneg_fold_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx4 s[0:3], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_load_dword v1, v0, s[2:3] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: v_pk_mul_f16 v1, v1, v1 neg_lo:[1,0] neg_hi:[1,0] |
| ; GFX9-NEXT: global_store_dword v0, v1, s[0:1] |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: v_fneg_fold_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_load_b32 v1, v0, s[2:3] |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) |
| ; GFX11-NEXT: v_pk_mul_f16 v1, v1, v1 neg_lo:[1,0] neg_hi:[1,0] |
| ; GFX11-NEXT: global_store_b32 v0, v1, s[0:1] |
| ; GFX11-NEXT: s_endpgm |
| %val = load <2 x half>, ptr addrspace(1) %in |
| %fsub = fsub <2 x half> <half -0.0, half -0.0>, %val |
| %fmul = fmul <2 x half> %fsub, %val |
| store <2 x half> %fmul, ptr addrspace(1) %out |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_extract_fneg_fold_v2f16(ptr addrspace(1) %in) #0 { |
| ; CI-LABEL: v_extract_fneg_fold_v2f16: |
| ; CI: ; %bb.0: |
| ; CI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CI-NEXT: flat_load_dword v0, v[0:1] |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f32_f16_e32 v1, v1 |
| ; CI-NEXT: v_mul_f32_e32 v0, -4.0, v0 |
| ; CI-NEXT: v_sub_f32_e32 v1, 2.0, v1 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v0, v0 |
| ; CI-NEXT: v_cvt_f16_f32_e32 v1, v1 |
| ; CI-NEXT: flat_store_short v[0:1], v0 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: flat_store_short v[0:1], v1 |
| ; CI-NEXT: s_waitcnt vmcnt(0) |
| ; CI-NEXT: s_endpgm |
| ; |
| ; GFX8-LABEL: v_extract_fneg_fold_v2f16: |
| ; GFX8: ; %bb.0: |
| ; GFX8-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX8-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX8-NEXT: v_mov_b32_e32 v0, s0 |
| ; GFX8-NEXT: v_mov_b32_e32 v1, s1 |
| ; GFX8-NEXT: flat_load_dword v0, v[0:1] |
| ; GFX8-NEXT: v_mov_b32_e32 v1, 0x4000 |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: v_mul_f16_e32 v2, -4.0, v0 |
| ; GFX8-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 |
| ; GFX8-NEXT: flat_store_short v[0:1], v2 |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: flat_store_short v[0:1], v0 |
| ; GFX8-NEXT: s_waitcnt vmcnt(0) |
| ; GFX8-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: v_extract_fneg_fold_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: v_mov_b32_e32 v1, 0x4000 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_load_dword v0, v0, s[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: v_mul_f16_e32 v2, -4.0, v0 |
| ; GFX9-NEXT: v_sub_f16_sdwa v0, v1, v0 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:WORD_1 |
| ; GFX9-NEXT: global_store_short v[0:1], v2, off |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: global_store_short v[0:1], v0, off |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: v_extract_fneg_fold_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) |
| ; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; GFX11-NEXT: v_mul_f16_e32 v0, -4.0, v0 |
| ; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) |
| ; GFX11-NEXT: v_sub_f16_e32 v1, 2.0, v1 |
| ; GFX11-NEXT: global_store_b16 v[0:1], v0, off dlc |
| ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 |
| ; GFX11-NEXT: global_store_b16 v[0:1], v1, off dlc |
| ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 |
| ; GFX11-NEXT: s_endpgm |
| %val = load <2 x half>, ptr addrspace(1) %in |
| %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val |
| %elt0 = extractelement <2 x half> %fneg, i32 0 |
| %elt1 = extractelement <2 x half> %fneg, i32 1 |
| |
| %fmul0 = fmul half %elt0, 4.0 |
| %fadd1 = fadd half %elt1, 2.0 |
| store volatile half %fmul0, ptr addrspace(1) undef |
| store volatile half %fadd1, ptr addrspace(1) undef |
| ret void |
| } |
| |
| define amdgpu_kernel void @v_extract_fneg_no_fold_v2f16(ptr addrspace(1) %in) #0 { |
| ; CIVI-LABEL: v_extract_fneg_no_fold_v2f16: |
| ; CIVI: ; %bb.0: |
| ; CIVI-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; CIVI-NEXT: s_waitcnt lgkmcnt(0) |
| ; CIVI-NEXT: v_mov_b32_e32 v0, s0 |
| ; CIVI-NEXT: v_mov_b32_e32 v1, s1 |
| ; CIVI-NEXT: flat_load_dword v0, v[0:1] |
| ; CIVI-NEXT: s_waitcnt vmcnt(0) |
| ; CIVI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 |
| ; CIVI-NEXT: v_lshrrev_b32_e32 v1, 16, v0 |
| ; CIVI-NEXT: flat_store_short v[0:1], v0 |
| ; CIVI-NEXT: s_waitcnt vmcnt(0) |
| ; CIVI-NEXT: flat_store_short v[0:1], v1 |
| ; CIVI-NEXT: s_waitcnt vmcnt(0) |
| ; CIVI-NEXT: s_endpgm |
| ; |
| ; GFX9-LABEL: v_extract_fneg_no_fold_v2f16: |
| ; GFX9: ; %bb.0: |
| ; GFX9-NEXT: s_load_dwordx2 s[0:1], s[8:9], 0x0 |
| ; GFX9-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX9-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX9-NEXT: global_load_dword v0, v0, s[0:1] |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 |
| ; GFX9-NEXT: global_store_short v[0:1], v0, off |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: global_store_short_d16_hi v[0:1], v0, off |
| ; GFX9-NEXT: s_waitcnt vmcnt(0) |
| ; GFX9-NEXT: s_endpgm |
| ; |
| ; GFX11-LABEL: v_extract_fneg_no_fold_v2f16: |
| ; GFX11: ; %bb.0: |
| ; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x0 |
| ; GFX11-NEXT: v_mov_b32_e32 v0, 0 |
| ; GFX11-NEXT: s_waitcnt lgkmcnt(0) |
| ; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] |
| ; GFX11-NEXT: s_waitcnt vmcnt(0) |
| ; GFX11-NEXT: v_xor_b32_e32 v0, 0x80008000, v0 |
| ; GFX11-NEXT: global_store_b16 v[0:1], v0, off dlc |
| ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 |
| ; GFX11-NEXT: global_store_d16_hi_b16 v[0:1], v0, off dlc |
| ; GFX11-NEXT: s_waitcnt_vscnt null, 0x0 |
| ; GFX11-NEXT: s_endpgm |
| %val = load <2 x half>, ptr addrspace(1) %in |
| %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val |
| %elt0 = extractelement <2 x half> %fneg, i32 0 |
| %elt1 = extractelement <2 x half> %fneg, i32 1 |
| store volatile half %elt0, ptr addrspace(1) undef |
| store volatile half %elt1, ptr addrspace(1) undef |
| ret void |
| } |
| |
| declare i32 @llvm.amdgcn.workitem.id.x() #1 |
| |
| attributes #0 = { nounwind } |
| attributes #1 = { nounwind readnone } |
