llvm/test/CodeGen/AMDGPU/blender-no-live-segment-at-def-implicit-def.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1031 -verify-coalescing < %s | FileCheck %s

define amdgpu_kernel void @blender_no_live_segment_at_def_error(<4 x float> %extractVec358.i.i, i32 %cmp5.i.i.arg, float %i1.i, i32 %cmp221.i.i.arg, i32 %cmp262.i.i.arg, ptr addrspace(1) %arg) {
; CHECK-LABEL: blender_no_live_segment_at_def_error:
; CHECK:       ; %bb.0: ; %entry
; CHECK-NEXT:    s_add_u32 s12, s12, s17
; CHECK-NEXT:    s_mov_b32 s32, 0
; CHECK-NEXT:    s_addc_u32 s13, s13, 0
; CHECK-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_LO), s12
; CHECK-NEXT:    s_setreg_b32 hwreg(HW_REG_FLAT_SCR_HI), s13
; CHECK-NEXT:    s_load_dwordx8 s[36:43], s[8:9], 0x0
; CHECK-NEXT:    s_add_u32 s0, s0, s17
; CHECK-NEXT:    s_addc_u32 s1, s1, 0
; CHECK-NEXT:    s_mov_b32 s12, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_cmp_lg_u32 s40, 0
; CHECK-NEXT:    s_cbranch_scc1 .LBB0_8
; CHECK-NEXT:  ; %bb.1: ; %if.end13.i.i
; CHECK-NEXT:    s_cmp_eq_u32 s42, 0
; CHECK-NEXT:    s_cbranch_scc1 .LBB0_4
; CHECK-NEXT:  ; %bb.2: ; %if.else251.i.i
; CHECK-NEXT:    s_cmp_lg_u32 s43, 0
; CHECK-NEXT:    s_mov_b32 s17, 0
; CHECK-NEXT:    s_cselect_b32 s12, -1, 0
; CHECK-NEXT:    s_and_b32 vcc_lo, exec_lo, s12
; CHECK-NEXT:    s_cbranch_vccz .LBB0_5
; CHECK-NEXT:  ; %bb.3:
; CHECK-NEXT:    s_mov_b32 s36, 0
; CHECK-NEXT:    s_andn2_b32 vcc_lo, exec_lo, s12
; CHECK-NEXT:    s_cbranch_vccz .LBB0_6
; CHECK-NEXT:    s_branch .LBB0_7
; CHECK-NEXT:  .LBB0_4:
; CHECK-NEXT:    s_mov_b32 s14, s12
; CHECK-NEXT:    s_mov_b32 s15, s12
; CHECK-NEXT:    s_mov_b32 s13, s12
; CHECK-NEXT:    s_mov_b64 s[38:39], s[14:15]
; CHECK-NEXT:    s_mov_b64 s[36:37], s[12:13]
; CHECK-NEXT:    s_branch .LBB0_7
; CHECK-NEXT:  .LBB0_5: ; %if.then263.i.i
; CHECK-NEXT:    v_cmp_lt_f32_e64 s12, s41, 0
; CHECK-NEXT:    s_mov_b32 s36, 1.0
; CHECK-NEXT:    s_mov_b32 s17, 0x7fc00000
; CHECK-NEXT:    s_mov_b32 s37, s36
; CHECK-NEXT:    s_mov_b32 s38, s36
; CHECK-NEXT:    s_mov_b32 s39, s36
; CHECK-NEXT:    s_andn2_b32 vcc_lo, exec_lo, s12
; CHECK-NEXT:    s_cbranch_vccnz .LBB0_7
; CHECK-NEXT:  .LBB0_6: ; %if.end273.i.i
; CHECK-NEXT:    s_add_u32 s12, s8, 40
; CHECK-NEXT:    s_addc_u32 s13, s9, 0
; CHECK-NEXT:    s_getpc_b64 s[18:19]
; CHECK-NEXT:    s_add_u32 s18, s18, _Z3dotDv3_fS_@gotpcrel32@lo+4
; CHECK-NEXT:    s_addc_u32 s19, s19, _Z3dotDv3_fS_@gotpcrel32@hi+12
; CHECK-NEXT:    v_lshlrev_b32_e32 v2, 20, v2
; CHECK-NEXT:    s_load_dwordx2 s[18:19], s[18:19], 0x0
; CHECK-NEXT:    v_lshlrev_b32_e32 v3, 10, v1
; CHECK-NEXT:    v_add_f32_e64 v1, s17, s36
; CHECK-NEXT:    s_mov_b64 s[34:35], s[8:9]
; CHECK-NEXT:    s_mov_b64 s[8:9], s[12:13]
; CHECK-NEXT:    s_mov_b32 s12, s14
; CHECK-NEXT:    v_or3_b32 v31, v0, v3, v2
; CHECK-NEXT:    v_mov_b32_e32 v0, v1
; CHECK-NEXT:    v_mov_b32_e32 v1, 0
; CHECK-NEXT:    v_mov_b32_e32 v2, 0
; CHECK-NEXT:    s_mov_b32 s13, s15
; CHECK-NEXT:    s_mov_b32 s14, s16
; CHECK-NEXT:    s_mov_b32 s36, 0
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    s_swappc_b64 s[30:31], s[18:19]
; CHECK-NEXT:    s_mov_b64 s[8:9], s[34:35]
; CHECK-NEXT:    s_mov_b32 s37, s36
; CHECK-NEXT:    s_mov_b32 s38, s36
; CHECK-NEXT:    s_mov_b32 s39, s36
; CHECK-NEXT:  .LBB0_7: ; %if.end294.i.i
; CHECK-NEXT:    v_mov_b32_e32 v0, 0
; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:12
; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:8
; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0 offset:4
; CHECK-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; CHECK-NEXT:  .LBB0_8: ; %kernel_direct_lighting.exit
; CHECK-NEXT:    s_load_dwordx2 s[4:5], s[8:9], 0x20
; CHECK-NEXT:    v_mov_b32_e32 v0, s36
; CHECK-NEXT:    v_mov_b32_e32 v4, 0
; CHECK-NEXT:    v_mov_b32_e32 v1, s37
; CHECK-NEXT:    v_mov_b32_e32 v2, s38
; CHECK-NEXT:    v_mov_b32_e32 v3, s39
; CHECK-NEXT:    s_waitcnt lgkmcnt(0)
; CHECK-NEXT:    global_store_dwordx4 v4, v[0:3], s[4:5]
; CHECK-NEXT:    s_endpgm
entry:
  %cmp5.i.i = icmp eq i32 %cmp5.i.i.arg, 0
  br i1 %cmp5.i.i, label %if.end13.i.i, label %kernel_direct_lighting.exit

if.end13.i.i:                                     ; preds = %entry
  %cmp221.i.i = icmp eq i32 %cmp221.i.i.arg, 0
  br i1 %cmp221.i.i, label %if.end294.i.i, label %if.else251.i.i

if.else251.i.i:                                   ; preds = %if.end13.i.i
  %cmp262.i.i = icmp eq i32 %cmp262.i.i.arg, 0
  br i1 %cmp262.i.i, label %if.then263.i.i, label %if.end273.i.i

if.then263.i.i:                                   ; preds = %if.else251.i.i
  %cmp.i604.i.i = fcmp olt float %i1.i, 0.000000e+00
  br i1 %cmp.i604.i.i, label %if.end273.i.i, label %if.end294.i.i

if.end273.i.i:                                    ; preds = %if.then263.i.i, %if.else251.i.i
  %i = phi float [ 1.000000e+00, %if.then263.i.i ], [ 0.000000e+00, %if.else251.i.i ]
  %i1 = phi float [ 0x7FF8000000000000, %if.then263.i.i ], [ 0.000000e+00, %if.else251.i.i ]
  %extractVec278.i.i = insertelement <3 x float> zeroinitializer, float %i1, i64 0
  %extractVec3.i.i.i = insertelement <3 x float> zeroinitializer, float %i, i64 0
  %i3.i = fadd <3 x float> %extractVec278.i.i, %extractVec3.i.i.i
  %call32.i.i.i = tail call float @_Z3dotDv3_fS_(<3 x float> %i3.i)
  br label %if.end294.i.i

if.end294.i.i:                                    ; preds = %if.end273.i.i, %if.then263.i.i, %if.end13.i.i
  %ls111.sroa.0.2.i = phi <4 x float> [ zeroinitializer, %if.end13.i.i ], [ zeroinitializer, %if.end273.i.i ], [ <float 1.000000e+00, float 1.000000e+00, float 1.000000e+00, float 1.000000e+00>, %if.then263.i.i ]
  store <4 x float> zeroinitializer, ptr addrspace(5) null, align 4
  br label %kernel_direct_lighting.exit

kernel_direct_lighting.exit:                      ; preds = %if.end294.i.i, %entry
  %ls111.sroa.0.3.i = phi <4 x float> [ %ls111.sroa.0.2.i, %if.end294.i.i ], [ %extractVec358.i.i, %entry ]
  store <4 x float> %ls111.sroa.0.3.i, ptr addrspace(1) %arg, align 4
  ret void
}

declare float @_Z3dotDv3_fS_(<3 x float>)

!llvm.module.flags = !{!0}
!0 = !{i32 1, !"amdhsa_code_object_version", i32 500}