| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=aarch64-- -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s |
| --- |
| name: test_f32 |
| alignment: 4 |
| exposesReturnsTwice: false |
| legalized: true |
| regBankSelected: true |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $s0, $s1, $s2, $s3 |
| |
| ; CHECK-LABEL: name: test_f32 |
| ; CHECK: liveins: $s0, $s1, $s2, $s3 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr32 = COPY $s1 |
| ; CHECK: [[COPY2:%[0-9]+]]:fpr32 = COPY $s2 |
| ; CHECK: [[COPY3:%[0-9]+]]:fpr32 = COPY $s3 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub |
| ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.ssub |
| ; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 |
| ; CHECK: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[COPY2]], %subreg.ssub |
| ; CHECK: [[INSvi32lane1:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane]], 2, [[INSERT_SUBREG2]], 0 |
| ; CHECK: [[DEF3:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG3:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF3]], [[COPY3]], %subreg.ssub |
| ; CHECK: [[INSvi32lane2:%[0-9]+]]:fpr128 = INSvi32lane [[INSvi32lane1]], 3, [[INSERT_SUBREG3]], 0 |
| ; CHECK: $q0 = COPY [[INSvi32lane2]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:fpr(s32) = COPY $s0 |
| %1:fpr(s32) = COPY $s1 |
| %2:fpr(s32) = COPY $s2 |
| %3:fpr(s32) = COPY $s3 |
| %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32) |
| $q0 = COPY %4(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: test_f64 |
| alignment: 4 |
| exposesReturnsTwice: false |
| legalized: true |
| regBankSelected: true |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $d0, $d1, $d2, $d3 |
| |
| ; CHECK-LABEL: name: test_f64 |
| ; CHECK: liveins: $d0, $d1, $d2, $d3 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0 |
| ; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub |
| ; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.dsub |
| ; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0 |
| ; CHECK: $q0 = COPY [[INSvi64lane]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:fpr(s64) = COPY $d0 |
| %1:fpr(s64) = COPY $d1 |
| %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64) |
| $q0 = COPY %4(<2 x s64>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: test_i32 |
| alignment: 4 |
| exposesReturnsTwice: false |
| legalized: true |
| regBankSelected: true |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $w0, $w1, $w2, $w3 |
| |
| ; CHECK-LABEL: name: test_i32 |
| ; CHECK: liveins: $w0, $w1, $w2, $w3 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr32all = COPY $w0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr32 = COPY $w1 |
| ; CHECK: [[COPY2:%[0-9]+]]:gpr32 = COPY $w2 |
| ; CHECK: [[COPY3:%[0-9]+]]:gpr32 = COPY $w3 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub |
| ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY1]] |
| ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, [[COPY2]] |
| ; CHECK: [[INSvi32gpr2:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, [[COPY3]] |
| ; CHECK: $q0 = COPY [[INSvi32gpr2]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:gpr(s32) = COPY $w0 |
| %1:gpr(s32) = COPY $w1 |
| %2:gpr(s32) = COPY $w2 |
| %3:gpr(s32) = COPY $w3 |
| %4:fpr(<4 x s32>) = G_BUILD_VECTOR %0(s32), %1(s32), %2(s32), %3(s32) |
| $q0 = COPY %4(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: test_i64 |
| alignment: 4 |
| exposesReturnsTwice: false |
| legalized: true |
| regBankSelected: true |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| |
| ; CHECK-LABEL: name: test_i64 |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub |
| ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]] |
| ; CHECK: $q0 = COPY [[INSvi64gpr]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:gpr(s64) = COPY $x0 |
| %1:gpr(s64) = COPY $x1 |
| %4:fpr(<2 x s64>) = G_BUILD_VECTOR %0(s64), %1(s64) |
| $q0 = COPY %4(<2 x s64>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: test_p0 |
| alignment: 4 |
| exposesReturnsTwice: false |
| legalized: true |
| regBankSelected: true |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| body: | |
| bb.0: |
| liveins: $x0, $x1 |
| |
| ; CHECK-LABEL: name: test_p0 |
| ; CHECK: liveins: $x0, $x1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr64all = COPY $x0 |
| ; CHECK: [[COPY1:%[0-9]+]]:gpr64 = COPY $x1 |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub |
| ; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[INSERT_SUBREG]], 1, [[COPY1]] |
| ; CHECK: $q0 = COPY [[INSvi64gpr]] |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %0:gpr(p0) = COPY $x0 |
| %1:gpr(p0) = COPY $x1 |
| %4:fpr(<2 x p0>) = G_BUILD_VECTOR %0(p0), %1(p0) |
| $q0 = COPY %4(<2 x p0>) |
| RET_ReallyLR implicit $q0 |
| |
| ... |
| --- |
| name: test_v4s32_zero |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$x0' } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: {} |
| body: | |
| bb.1: |
| liveins: $x0 |
| |
| ; CHECK-LABEL: name: test_v4s32_zero |
| ; CHECK: liveins: $x0 |
| ; CHECK: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 |
| ; CHECK: $q0 = COPY [[MOVIv2d_ns]] |
| ; CHECK: RET_ReallyLR |
| %0:gpr(p0) = COPY $x0 |
| %2:gpr(s32) = G_CONSTANT i32 0 |
| %3:fpr(s32) = COPY %2(s32) |
| %4:fpr(s32) = COPY %2(s32) |
| %5:fpr(s32) = COPY %2(s32) |
| %6:fpr(s32) = COPY %2(s32) |
| %1:fpr(<4 x s32>) = G_BUILD_VECTOR %3(s32), %4(s32), %5(s32), %6(s32) |
| $q0 = COPY %1(<4 x s32>) |
| RET_ReallyLR |
| ... |
| --- |
| name: test_v8s8_zero |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| liveins: |
| - { reg: '$x0' } |
| frameInfo: |
| maxAlignment: 1 |
| machineFunctionInfo: {} |
| body: | |
| bb.1: |
| liveins: $x0 |
| |
| ; CHECK-LABEL: name: test_v8s8_zero |
| ; CHECK: liveins: $x0 |
| ; CHECK: [[MOVIv2d_ns:%[0-9]+]]:fpr128 = MOVIv2d_ns 0 |
| ; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY [[MOVIv2d_ns]].dsub |
| ; CHECK: $d0 = COPY [[COPY]] |
| ; CHECK: RET_ReallyLR |
| %0:gpr(p0) = COPY $x0 |
| %2:gpr(s8) = G_CONSTANT i8 0 |
| %3:fpr(s8) = COPY %2(s8) |
| %4:fpr(s8) = COPY %2(s8) |
| %5:fpr(s8) = COPY %2(s8) |
| %6:fpr(s8) = COPY %2(s8) |
| %7:fpr(s8) = COPY %2(s8) |
| %8:fpr(s8) = COPY %2(s8) |
| %9:fpr(s8) = COPY %2(s8) |
| %10:fpr(s8) = COPY %2(s8) |
| %1:fpr(<8 x s8>) = G_BUILD_VECTOR %3(s8), %4(s8), %5(s8), %6(s8), %7(s8), %8(s8), %9(s8), %10(s8) |
| $d0 = COPY %1(<8 x s8>) |
| RET_ReallyLR |
| ... |
| --- |
| name: undef_elts_to_subreg_to_reg |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $s0 |
| ; We have a BUILD_VECTOR whose 0th element is a subregister of the wide |
| ; register class. Everything else is undef. This is a SUBREG_TO_REG. |
| |
| ; CHECK-LABEL: name: undef_elts_to_subreg_to_reg |
| ; CHECK: liveins: $s0 |
| ; CHECK: %val:fpr32 = COPY $s0 |
| ; CHECK: %bv:fpr128 = SUBREG_TO_REG 0, %val, %subreg.ssub |
| ; CHECK: $q0 = COPY %bv |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %val:fpr(s32) = COPY $s0 |
| %undef:fpr(s32) = G_IMPLICIT_DEF |
| %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32) |
| $q0 = COPY %bv(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| ... |
| ... |
| --- |
| name: undef_elts_different_regbanks |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $w0 |
| ; Element is not a subregister of the wide register class. This is not a |
| ; SUBREG_TO_REG. |
| |
| ; CHECK-LABEL: name: undef_elts_different_regbanks |
| ; CHECK: liveins: $w0 |
| ; CHECK: %val:gpr32all = COPY $w0 |
| ; CHECK: %undef:gpr32 = IMPLICIT_DEF |
| ; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF |
| ; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], %val, %subreg.ssub |
| ; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, %undef |
| ; CHECK: [[INSvi32gpr1:%[0-9]+]]:fpr128 = INSvi32gpr [[INSvi32gpr]], 2, %undef |
| ; CHECK: %bv:fpr128 = INSvi32gpr [[INSvi32gpr1]], 3, %undef |
| ; CHECK: $q0 = COPY %bv |
| ; CHECK: RET_ReallyLR implicit $q0 |
| %val:gpr(s32) = COPY $w0 |
| %undef:gpr(s32) = G_IMPLICIT_DEF |
| %bv:fpr(<4 x s32>) = G_BUILD_VECTOR %val(s32), %undef(s32), %undef(s32), %undef(s32) |
| $q0 = COPY %bv(<4 x s32>) |
| RET_ReallyLR implicit $q0 |
| ... |