llvm/test/CodeGen/RISCV/rvv/no-reserved-frame.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -verify-machineinstrs \
; RUN:   < %s | FileCheck %s

define signext i32 @foo(i32 signext %aa) #0 {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    addi sp, sp, -80
; CHECK-NEXT:    .cfi_def_cfa_offset 80
; CHECK-NEXT:    sd ra, 72(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s0, 64(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s1, 56(sp) # 8-byte Folded Spill
; CHECK-NEXT:    .cfi_offset ra, -8
; CHECK-NEXT:    .cfi_offset s0, -16
; CHECK-NEXT:    .cfi_offset s1, -24
; CHECK-NEXT:    addi s0, sp, 80
; CHECK-NEXT:    .cfi_def_cfa s0, 0
; CHECK-NEXT:    csrr a1, vlenb
; CHECK-NEXT:    sub sp, sp, a1
; CHECK-NEXT:    andi sp, sp, -8
; CHECK-NEXT:    mv s1, sp
; CHECK-NEXT:    lw t0, 44(s1)
; CHECK-NEXT:    lw a2, 40(s1)
; CHECK-NEXT:    lw a3, 36(s1)
; CHECK-NEXT:    lw a4, 32(s1)
; CHECK-NEXT:    lw a5, 28(s1)
; CHECK-NEXT:    lw a6, 24(s1)
; CHECK-NEXT:    lw a7, 20(s1)
; CHECK-NEXT:    lw t1, 16(s1)
; CHECK-NEXT:    lw t2, 12(s1)
; CHECK-NEXT:    lw a1, 8(s1)
; CHECK-NEXT:    sw a0, 52(s1)
; CHECK-NEXT:    sw a0, 48(s1)
; CHECK-NEXT:    addi sp, sp, -32
; CHECK-NEXT:    sd a1, 16(sp)
; CHECK-NEXT:    sd t2, 8(sp)
; CHECK-NEXT:    addi a1, s1, 48
; CHECK-NEXT:    sd t1, 0(sp)
; CHECK-NEXT:    mv a0, t0
; CHECK-NEXT:    call gfunc@plt
; CHECK-NEXT:    addi sp, sp, 32
; CHECK-NEXT:    li a0, 0
; CHECK-NEXT:    addi sp, s0, -80
; CHECK-NEXT:    ld ra, 72(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s0, 64(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s1, 56(sp) # 8-byte Folded Reload
; CHECK-NEXT:    addi sp, sp, 80
; CHECK-NEXT:    ret
entry:
  %aa.addr = alloca i32, align 4
  %local = alloca i32, align 4
  %a = alloca i32, align 4
  %b = alloca i32, align 4
  %c = alloca i32, align 4
  %d = alloca i32, align 4
  %e = alloca i32, align 4
  %f = alloca i32, align 4
  %g = alloca i32, align 4
  %h = alloca i32, align 4
  %i = alloca i32, align 4
  %j = alloca i32, align 4
  %local_v = alloca <vscale x 2 x i32>, align 4
  store i32 %aa, i32* %aa.addr, align 4
  %0 = load i32, i32* %aa.addr, align 4
  store i32 %0, i32* %local, align 4
  %1 = load i32, i32* %a, align 4
  %2 = load i32, i32* %b, align 4
  %3 = load i32, i32* %c, align 4
  %4 = load i32, i32* %d, align 4
  %5 = load i32, i32* %e, align 4
  %6 = load i32, i32* %f, align 4
  %7 = load i32, i32* %g, align 4
  %8 = load i32, i32* %h, align 4
  %9 = load i32, i32* %i, align 4
  %10 = load i32, i32* %j, align 4
  call void @gfunc(i32 signext %1, i32* %local, i32 signext %2, i32 signext %3, i32 signext %4, i32 signext %5, i32 signext %6, i32 signext %7, i32 %8, i32 %9, i32 %10)
  ret i32 0
}

declare void @gfunc(i32 signext, i32*, i32 signext, i32 signext, i32 signext, i32 signext, i32 signext, i32 signext, i32, i32, i32) #1

attributes #0 = { "stackrealign" }
attributes #1 = { "stackrealign" }