Revert "[AArch64] Fold scalar-to-vector shuffles into DUP/FMOV" (#175123)
Reverts llvm/llvm-project#166962
Causes compile time issues in a tensorflow kernel. See the original PR
for discussion.
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 7c041a4..ef0136d 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -16035,39 +16035,6 @@
}
}
- // 128-bit NEON vectors: writing to the 64-bit low half with
- // DUP/SCALAR_TO_VECTOR already zeroes the other 64 bits, so if the low half
- // is a splat and the upper half is zero/undef we can materialise just that
- // low half.
- if (VT.isFixedLengthVector() && VT.getSizeInBits() == 128) {
- EVT LaneVT = VT.getVectorElementType();
- const unsigned HalfElts = NumElts >> 1;
- SDValue FirstVal = Op.getOperand(0);
-
- auto IsZero = [&](SDValue V) {
- return isNullConstant(V) || isNullFPConstant(V);
- };
-
- if (llvm::all_of(llvm::seq<unsigned>(0, NumElts), [&](unsigned I) {
- SDValue Vi = Op.getOperand(I);
- return I < HalfElts ? (Vi == FirstVal) : IsZero(Vi);
- })) {
- EVT HalfVT = VT.getHalfNumVectorElementsVT(*DAG.getContext());
-
- SDValue HiZero = LaneVT.isInteger() ? DAG.getConstant(0, DL, HalfVT)
- : DAG.getConstantFP(0.0, DL, HalfVT);
-
- SDValue LoHalf =
- LaneVT.getSizeInBits() == 64
- // 64-bit lanes lower to an FMOV via SCALAR_TO_VECTOR.
- ? DAG.getNode(ISD::SCALAR_TO_VECTOR, DL, HalfVT, FirstVal)
- // Smaller lanes need DUP to splat the whole low half.
- : DAG.getNode(AArch64ISD::DUP, DL, HalfVT, FirstVal);
-
- return DAG.getNode(ISD::CONCAT_VECTORS, DL, VT, LoHalf, HiZero);
- }
- }
-
// Use DUP for non-constant splats. For f32 constant splats, reduce to
// i32 and try again.
if (usesOnlyOneValue) {
diff --git a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
index b39ea8c..d25db89 100644
--- a/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
+++ b/llvm/lib/Target/AArch64/AArch64MIPeepholeOpt.cpp
@@ -688,57 +688,14 @@
}
// All instructions that set a FPR64 will implicitly zero the top bits of the
-// register. When the def is expressed as a COPY from a GPR, turn it into an
-// explicit FMOV so it cannot be elided later in further passes.
+// register.
static bool is64bitDefwithZeroHigh64bit(MachineInstr *MI,
- MachineRegisterInfo *MRI,
- const AArch64InstrInfo *TII) {
+ MachineRegisterInfo *MRI) {
if (!MI->getOperand(0).isReg() || !MI->getOperand(0).isDef())
return false;
const TargetRegisterClass *RC = MRI->getRegClass(MI->getOperand(0).getReg());
if (RC != &AArch64::FPR64RegClass)
return false;
- if (MI->getOpcode() == TargetOpcode::COPY) {
- MachineOperand &SrcOp = MI->getOperand(1);
- if (!SrcOp.isReg())
- return false;
- if (SrcOp.getSubReg())
- return false;
- Register SrcReg = SrcOp.getReg();
- auto IsGPR64Like = [&]() -> bool {
- if (SrcReg.isVirtual())
- return AArch64::GPR64allRegClass.hasSubClassEq(
- MRI->getRegClass(SrcReg));
- return AArch64::GPR64allRegClass.contains(SrcReg);
- };
- if (!IsGPR64Like())
- return false;
- assert(TII && "Expected InstrInfo when materializing COPYs");
- // FMOVXDr insists on strict GPR64 operands, so fix up the COPY source.
- MachineOperand &SrcMO = MI->getOperand(1);
- bool SrcKill = SrcMO.isKill();
- if (SrcReg.isVirtual()) {
- if (MRI->getRegClass(SrcReg) != &AArch64::GPR64RegClass) {
- // Pass the value through a temporary GPR64 vreg to satisfy the
- // verifier.
- Register NewSrc = MRI->createVirtualRegister(&AArch64::GPR64RegClass);
- BuildMI(*MI->getParent(), MI, MI->getDebugLoc(),
- TII->get(TargetOpcode::COPY), NewSrc)
- .addReg(SrcReg, getKillRegState(SrcKill));
- SrcReg = NewSrc;
- SrcKill = true;
- }
- } else if (!AArch64::GPR64RegClass.contains(SrcReg)) {
- return false;
- }
- SrcMO.setReg(SrcReg);
- SrcMO.setSubReg(0);
- SrcMO.setIsKill(SrcKill);
- // Replace the COPY with an explicit FMOV so the zeroing behaviour stays
- // visible.
- MI->setDesc(TII->get(AArch64::FMOVXDr));
- return true;
- }
return MI->getOpcode() > TargetOpcode::GENERIC_OP_END;
}
@@ -754,7 +711,7 @@
if (Low64MI->getOpcode() != AArch64::INSERT_SUBREG)
return false;
Low64MI = MRI->getUniqueVRegDef(Low64MI->getOperand(2).getReg());
- if (!Low64MI || !is64bitDefwithZeroHigh64bit(Low64MI, MRI, TII))
+ if (!Low64MI || !is64bitDefwithZeroHigh64bit(Low64MI, MRI))
return false;
// Check there is `mov 0` MI for high 64-bits.
@@ -795,7 +752,7 @@
bool AArch64MIPeepholeOpt::visitFMOVDr(MachineInstr &MI) {
// An FMOVDr sets the high 64-bits to zero implicitly, similar to ORR for GPR.
MachineInstr *Low64MI = MRI->getUniqueVRegDef(MI.getOperand(1).getReg());
- if (!Low64MI || !is64bitDefwithZeroHigh64bit(Low64MI, MRI, TII))
+ if (!Low64MI || !is64bitDefwithZeroHigh64bit(Low64MI, MRI))
return false;
// Let's remove MIs for high 64-bits.
diff --git a/llvm/test/CodeGen/AArch64/aarch64-addv.ll b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
index 94219ee1..d9180a2 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-addv.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-addv.ll
@@ -553,8 +553,9 @@
define i8 @addv_zero_lanes_v16i8(ptr %arr) {
; CHECK-SD-LABEL: addv_zero_lanes_v16i8:
; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
; CHECK-SD-NEXT: ldrb w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: mov v0.d[0], x8
; CHECK-SD-NEXT: addv b0, v0.16b
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
@@ -577,8 +578,9 @@
define i16 @addv_zero_lanes_v8i16(ptr %arr) {
; CHECK-SD-LABEL: addv_zero_lanes_v8i16:
; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
; CHECK-SD-NEXT: ldrh w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: mov v0.d[0], x8
; CHECK-SD-NEXT: addv h0, v0.8h
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
@@ -601,8 +603,9 @@
define i32 @addv_zero_lanes_v4i32(ptr %arr) {
; CHECK-SD-LABEL: addv_zero_lanes_v4i32:
; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
; CHECK-SD-NEXT: ldr w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: mov v0.d[0], x8
; CHECK-SD-NEXT: addv s0, v0.4s
; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
index a1c7c4a..99c5403 100644
--- a/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
+++ b/llvm/test/CodeGen/AArch64/aarch64-matrix-umull-smull.ll
@@ -823,14 +823,15 @@
; CHECK-SD-NEXT: // %bb.9: // %vec.epilog.iter.check
; CHECK-SD-NEXT: cbz x11, .LBB6_13
; CHECK-SD-NEXT: .LBB6_10: // %vec.epilog.ph
-; CHECK-SD-NEXT: mov w11, w1
; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
-; CHECK-SD-NEXT: movi v3.2d, #0x000000000000ff
+; CHECK-SD-NEXT: mov w11, w1
+; CHECK-SD-NEXT: movi v1.2d, #0000000000000000
; CHECK-SD-NEXT: sxtb x11, w11
-; CHECK-SD-NEXT: fmov d2, x8
-; CHECK-SD-NEXT: dup v1.2s, w11
+; CHECK-SD-NEXT: movi v3.2d, #0x000000000000ff
+; CHECK-SD-NEXT: dup v2.2s, w11
; CHECK-SD-NEXT: mov x11, x10
; CHECK-SD-NEXT: and x10, x9, #0xfffffffc
+; CHECK-SD-NEXT: mov v0.d[0], x8
; CHECK-SD-NEXT: sub x8, x11, x10
; CHECK-SD-NEXT: add x11, x0, x11
; CHECK-SD-NEXT: .LBB6_11: // %vec.epilog.vector.body
@@ -845,11 +846,11 @@
; CHECK-SD-NEXT: and v4.16b, v4.16b, v3.16b
; CHECK-SD-NEXT: xtn v5.2s, v5.2d
; CHECK-SD-NEXT: xtn v4.2s, v4.2d
-; CHECK-SD-NEXT: smlal v0.2d, v1.2s, v4.2s
-; CHECK-SD-NEXT: smlal v2.2d, v1.2s, v5.2s
+; CHECK-SD-NEXT: smlal v1.2d, v2.2s, v4.2s
+; CHECK-SD-NEXT: smlal v0.2d, v2.2s, v5.2s
; CHECK-SD-NEXT: b.ne .LBB6_11
; CHECK-SD-NEXT: // %bb.12: // %vec.epilog.middle.block
-; CHECK-SD-NEXT: add v0.2d, v2.2d, v0.2d
+; CHECK-SD-NEXT: add v0.2d, v0.2d, v1.2d
; CHECK-SD-NEXT: cmp x10, x9
; CHECK-SD-NEXT: addp d0, v0.2d
; CHECK-SD-NEXT: fmov x8, d0
diff --git a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
index 5af21da..bae254b 100644
--- a/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-vector-insertion.ll
@@ -318,7 +318,10 @@
define <2 x double> @test_insert_v2f64_undef_insert1(double %a) {
; CHECK-LABEL: test_insert_v2f64_undef_insert1:
; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d0, d0
+; CHECK-NEXT: movi.2d v1, #0000000000000000
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: mov.d v1[0], v0[0]
+; CHECK-NEXT: mov.16b v0, v1
; CHECK-NEXT: ret
%v.0 = insertelement <2 x double > <double undef, double 0.000000e+00>, double %a, i32 0
ret <2 x double> %v.0
diff --git a/llvm/test/CodeGen/AArch64/bitcast-extend.ll b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
index b981c17..741dcf3 100644
--- a/llvm/test/CodeGen/AArch64/bitcast-extend.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast-extend.ll
@@ -339,8 +339,9 @@
define <16 x i8> @load_zext_v16i8(ptr %p) {
; CHECK-SD-LABEL: load_zext_v16i8:
; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
; CHECK-SD-NEXT: ldr w8, [x0]
-; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: mov v0.d[0], x8
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: load_zext_v16i8:
diff --git a/llvm/test/CodeGen/AArch64/combine-sdiv.ll b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
index 7e47c68..d15f6e2 100644
--- a/llvm/test/CodeGen/AArch64/combine-sdiv.ll
+++ b/llvm/test/CodeGen/AArch64/combine-sdiv.ll
@@ -578,10 +578,10 @@
; CHECK-SD-NEXT: adrp x8, .LCPI21_1
; CHECK-SD-NEXT: ushl v1.2d, v1.2d, v2.2d
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI21_1]
-; CHECK-SD-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-SD-NEXT: adrp x8, .LCPI21_2
; CHECK-SD-NEXT: add v1.2d, v0.2d, v1.2d
; CHECK-SD-NEXT: sshl v1.2d, v1.2d, v2.2d
-; CHECK-SD-NEXT: fmov d2, x8
+; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI21_2]
; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: ret
;
@@ -613,20 +613,20 @@
; CHECK-SD-NEXT: adrp x8, .LCPI22_0
; CHECK-SD-NEXT: cmlt v2.2d, v0.2d, #0
; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI22_0]
-; CHECK-SD-NEXT: adrp x8, .LCPI22_2
-; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_2]
+; CHECK-SD-NEXT: adrp x8, .LCPI22_3
+; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_3]
; CHECK-SD-NEXT: adrp x8, .LCPI22_1
; CHECK-SD-NEXT: ushl v2.2d, v2.2d, v3.2d
; CHECK-SD-NEXT: cmlt v3.2d, v1.2d, #0
; CHECK-SD-NEXT: add v2.2d, v0.2d, v2.2d
; CHECK-SD-NEXT: ushl v3.2d, v3.2d, v4.2d
; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_1]
-; CHECK-SD-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-SD-NEXT: adrp x8, .LCPI22_2
; CHECK-SD-NEXT: sshl v2.2d, v2.2d, v4.2d
-; CHECK-SD-NEXT: fmov d4, x8
+; CHECK-SD-NEXT: ldr q4, [x8, :lo12:.LCPI22_2]
; CHECK-SD-NEXT: add v1.2d, v1.2d, v3.2d
-; CHECK-SD-NEXT: adrp x8, .LCPI22_3
-; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI22_3]
+; CHECK-SD-NEXT: adrp x8, .LCPI22_4
+; CHECK-SD-NEXT: ldr q3, [x8, :lo12:.LCPI22_4]
; CHECK-SD-NEXT: bif v0.16b, v2.16b, v4.16b
; CHECK-SD-NEXT: sshl v1.2d, v1.2d, v3.2d
; CHECK-SD-NEXT: ret
@@ -670,26 +670,26 @@
; CHECK-SD-NEXT: cmlt v4.2d, v0.2d, #0
; CHECK-SD-NEXT: cmlt v6.2d, v2.2d, #0
; CHECK-SD-NEXT: ldr q5, [x8, :lo12:.LCPI23_0]
-; CHECK-SD-NEXT: adrp x8, .LCPI23_2
+; CHECK-SD-NEXT: adrp x8, .LCPI23_3
; CHECK-SD-NEXT: cmlt v7.2d, v3.2d, #0
-; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI23_2]
+; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI23_3]
; CHECK-SD-NEXT: adrp x8, .LCPI23_1
; CHECK-SD-NEXT: ushl v4.2d, v4.2d, v5.2d
; CHECK-SD-NEXT: ushl v5.2d, v6.2d, v5.2d
; CHECK-SD-NEXT: cmlt v6.2d, v1.2d, #0
; CHECK-SD-NEXT: ldr q17, [x8, :lo12:.LCPI23_1]
; CHECK-SD-NEXT: ushl v7.2d, v7.2d, v16.2d
-; CHECK-SD-NEXT: mov x8, #-1 // =0xffffffffffffffff
+; CHECK-SD-NEXT: adrp x8, .LCPI23_2
; CHECK-SD-NEXT: add v4.2d, v0.2d, v4.2d
; CHECK-SD-NEXT: add v5.2d, v2.2d, v5.2d
; CHECK-SD-NEXT: ushl v6.2d, v6.2d, v16.2d
-; CHECK-SD-NEXT: fmov d16, x8
-; CHECK-SD-NEXT: adrp x8, .LCPI23_3
+; CHECK-SD-NEXT: ldr q16, [x8, :lo12:.LCPI23_2]
+; CHECK-SD-NEXT: adrp x8, .LCPI23_4
; CHECK-SD-NEXT: add v3.2d, v3.2d, v7.2d
; CHECK-SD-NEXT: sshl v4.2d, v4.2d, v17.2d
; CHECK-SD-NEXT: sshl v5.2d, v5.2d, v17.2d
; CHECK-SD-NEXT: add v1.2d, v1.2d, v6.2d
-; CHECK-SD-NEXT: ldr q6, [x8, :lo12:.LCPI23_3]
+; CHECK-SD-NEXT: ldr q6, [x8, :lo12:.LCPI23_4]
; CHECK-SD-NEXT: bif v0.16b, v4.16b, v16.16b
; CHECK-SD-NEXT: bif v2.16b, v5.16b, v16.16b
; CHECK-SD-NEXT: sshl v1.2d, v1.2d, v6.2d
@@ -920,13 +920,13 @@
; CHECK-SD-NEXT: adrp x8, .LCPI27_1
; CHECK-SD-NEXT: ushl v1.4s, v1.4s, v2.4s
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_1]
-; CHECK-SD-NEXT: mov w8, #-1 // =0xffffffff
-; CHECK-SD-NEXT: dup v3.2s, w8
; CHECK-SD-NEXT: adrp x8, .LCPI27_2
; CHECK-SD-NEXT: add v1.4s, v0.4s, v1.4s
; CHECK-SD-NEXT: sshl v1.4s, v1.4s, v2.4s
; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_2]
-; CHECK-SD-NEXT: bif v0.16b, v1.16b, v3.16b
+; CHECK-SD-NEXT: adrp x8, .LCPI27_3
+; CHECK-SD-NEXT: bif v0.16b, v1.16b, v2.16b
+; CHECK-SD-NEXT: ldr q2, [x8, :lo12:.LCPI27_3]
; CHECK-SD-NEXT: neg v1.4s, v0.4s
; CHECK-SD-NEXT: bit v0.16b, v1.16b, v2.16b
; CHECK-SD-NEXT: ret
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index 84984c2..9c59f1b 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -599,9 +599,10 @@
define i128 @i128_mask(i128 %x) {
; CHECK-SD-LABEL: i128_mask:
; CHECK-SD: // %bb.0: // %entry
+; CHECK-SD-NEXT: movi v0.2d, #0000000000000000
; CHECK-SD-NEXT: and x8, x0, #0xff
; CHECK-SD-NEXT: mov x1, xzr
-; CHECK-SD-NEXT: fmov d0, x8
+; CHECK-SD-NEXT: mov v0.d[0], x8
; CHECK-SD-NEXT: cnt v0.16b, v0.16b
; CHECK-SD-NEXT: addv b0, v0.16b
; CHECK-SD-NEXT: fmov x0, d0
diff --git a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
index 137a7fe..fd7c869 100644
--- a/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/fpclamptosat_vec.ll
@@ -829,9 +829,9 @@
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d0, x8
-; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -858,9 +858,9 @@
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d0, x8
-; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -1296,9 +1296,9 @@
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d0, x8
-; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -1326,9 +1326,9 @@
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d0, x8
-; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -1748,9 +1748,9 @@
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d0, x8
-; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -1778,9 +1778,9 @@
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d0, x8
-; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -2774,9 +2774,9 @@
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d0, x8
-; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -2803,9 +2803,9 @@
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d0, x8
-; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -3232,9 +3232,9 @@
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d0, x8
-; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -3262,9 +3262,9 @@
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d0, x8
-; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
@@ -3675,9 +3675,9 @@
; CHECK-CVT-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-CVT-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-CVT-SD-NEXT: cmp x20, #0
+; CHECK-CVT-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-CVT-SD-NEXT: fmov d0, x8
-; CHECK-CVT-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-CVT-SD-NEXT: fmov d1, x8
+; CHECK-CVT-SD-NEXT: fmov d1, x9
; CHECK-CVT-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-CVT-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-CVT-SD-NEXT: add sp, sp, #48
@@ -3705,9 +3705,9 @@
; CHECK-FP16-SD-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-FP16-SD-NEXT: csel x8, x0, xzr, eq
; CHECK-FP16-SD-NEXT: cmp x20, #0
+; CHECK-FP16-SD-NEXT: csel x9, x19, xzr, eq
; CHECK-FP16-SD-NEXT: fmov d0, x8
-; CHECK-FP16-SD-NEXT: csel x8, x19, xzr, eq
-; CHECK-FP16-SD-NEXT: fmov d1, x8
+; CHECK-FP16-SD-NEXT: fmov d1, x9
; CHECK-FP16-SD-NEXT: ldp x20, x19, [sp, #32] // 16-byte Folded Reload
; CHECK-FP16-SD-NEXT: mov v0.d[1], v1.d[0]
; CHECK-FP16-SD-NEXT: add sp, sp, #48
diff --git a/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll b/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
index c7e22b2..adde542 100644
--- a/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
+++ b/llvm/test/CodeGen/AArch64/implicitly-set-zero-high-64-bits.ll
@@ -95,7 +95,10 @@
define <2 x double> @fadd(double noundef %x, double noundef %y) {
; CHECK-LABEL: fadd:
; CHECK: // %bb.0: // %entry
+; CHECK-NEXT: movi v2.2d, #0000000000000000
; CHECK-NEXT: fadd d0, d0, d1
+; CHECK-NEXT: mov v2.d[0], v0.d[0]
+; CHECK-NEXT: mov v0.16b, v2.16b
; CHECK-NEXT: ret
entry:
%add = fadd double %x, %y
diff --git a/llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll b/llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll
deleted file mode 100644
index 38be299..0000000
--- a/llvm/test/CodeGen/AArch64/neon-lowhalf128-optimisation.ll
+++ /dev/null
@@ -1,91 +0,0 @@
-; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
-; RUN: llc -mtriple=aarch64-linux-gnu -o - %s | FileCheck %s
-
-define <2 x i64> @low_vector_splat_v2i64_from_i64(i64 %0){
-; CHECK-LABEL: low_vector_splat_v2i64_from_i64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d0, x0
-; CHECK-NEXT: ret
- %2 = insertelement <1 x i64> poison, i64 %0, i64 0
- %3 = shufflevector <1 x i64> %2, <1 x i64> zeroinitializer, <2 x i32> <i32 0, i32 1>
- ret <2 x i64> %3
-}
-
-define <4 x i32> @low_vector_splat_v4i32_from_i32(i32 %0) {
-; CHECK-LABEL: low_vector_splat_v4i32_from_i32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup v0.2s, w0
-; CHECK-NEXT: ret
- %2 = insertelement <2 x i32> poison, i32 %0, i64 0
- %3 = shufflevector <2 x i32> %2, <2 x i32> poison, <2 x i32> zeroinitializer
- %4 = shufflevector <2 x i32> %3, <2 x i32> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x i32> %4
-}
-
-define <8 x i16> @low_vector_splat_v8i16_from_i16(i16 %0) {
-; CHECK-LABEL: low_vector_splat_v8i16_from_i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup v0.4h, w0
-; CHECK-NEXT: ret
- %2 = insertelement <4 x i16> poison, i16 %0, i64 0
- %3 = shufflevector <4 x i16> %2, <4 x i16> poison, <4 x i32> zeroinitializer
- %4 = shufflevector <4 x i16> %3, <4 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x i16> %4
-}
-
-define <16 x i8> @low_vector_splat_v16i8_from_i8(i8 %0) {
-; CHECK-LABEL: low_vector_splat_v16i8_from_i8:
-; CHECK: // %bb.0:
-; CHECK-NEXT: dup v0.8b, w0
-; CHECK-NEXT: ret
- %2 = insertelement <8 x i8> poison, i8 %0, i64 0
- %3 = shufflevector <8 x i8> %2, <8 x i8> poison, <8 x i32> zeroinitializer
- %4 = shufflevector <8 x i8> %3, <8 x i8> zeroinitializer, <16 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7, i32 8, i32 9, i32 10, i32 11, i32 12, i32 13, i32 14, i32 15>
- ret <16 x i8> %4
-}
-
-define <2 x double> @low_vector_splat_v2f64_from_f64(double %0) {
-; CHECK-LABEL: low_vector_splat_v2f64_from_f64:
-; CHECK: // %bb.0:
-; CHECK-NEXT: fmov d0, d0
-; CHECK-NEXT: ret
- %2 = insertelement <1 x double> poison, double %0, i64 0
- %3 = shufflevector <1 x double> %2, <1 x double> zeroinitializer, <2 x i32> <i32 0, i32 1>
- ret <2 x double> %3
-}
-
-define <4 x float> @low_vector_splat_v4f32_from_f32(float %0) {
-; CHECK-LABEL: low_vector_splat_v4f32_from_f32:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $s0 killed $s0 def $q0
-; CHECK-NEXT: dup v0.2s, v0.s[0]
-; CHECK-NEXT: ret
- %2 = insertelement <2 x float> poison, float %0, i64 0
- %3 = shufflevector <2 x float> %2, <2 x float> poison, <2 x i32> zeroinitializer
- %4 = shufflevector <2 x float> %3, <2 x float> zeroinitializer, <4 x i32> <i32 0, i32 1, i32 2, i32 3>
- ret <4 x float> %4
-}
-
-define <8 x half> @low_vector_splat_v8f16_from_f16(half %0) {
-; CHECK-LABEL: low_vector_splat_v8f16_from_f16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-NEXT: dup v0.4h, v0.h[0]
-; CHECK-NEXT: ret
- %2 = insertelement <4 x half> poison, half %0, i64 0
- %3 = shufflevector <4 x half> %2, <4 x half> poison, <4 x i32> zeroinitializer
- %4 = shufflevector <4 x half> %3, <4 x half> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x half> %4
-}
-
-define <8 x bfloat> @low_vector_splat_v8bf16_from_bf16(bfloat %0) {
-; CHECK-LABEL: low_vector_splat_v8bf16_from_bf16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $h0 killed $h0 def $q0
-; CHECK-NEXT: dup v0.4h, v0.h[0]
-; CHECK-NEXT: ret
- %2 = insertelement <4 x bfloat> poison, bfloat %0, i64 0
- %3 = shufflevector <4 x bfloat> %2, <4 x bfloat> poison, <4 x i32> zeroinitializer
- %4 = shufflevector <4 x bfloat> %3, <4 x bfloat> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 7>
- ret <8 x bfloat> %4
-}
diff --git a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
index a68eda1..aef01e4 100644
--- a/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
+++ b/llvm/test/CodeGen/AArch64/peephole-insvigpr.mir
@@ -41,11 +41,6 @@
ret void
}
- define void @insert_vec_from_gpr64_zero_high(i64 %v, ptr %dst) {
- entry:
- ret void
- }
-
attributes #0 = { nocallback nofree nosync nounwind willreturn memory(none) }
...
@@ -526,50 +521,4 @@
STRSui killed %16, %0, 0 :: (store (s32) into %ir.hist)
RET_ReallyLR
----
-name: insert_vec_from_gpr64_zero_high
-tracksRegLiveness: true
-registers:
- - { id: 0, class: gpr64common, preferred-register: '' }
- - { id: 1, class: gpr64common, preferred-register: '' }
- - { id: 2, class: fpr64, preferred-register: '' }
- - { id: 3, class: fpr128, preferred-register: '' }
- - { id: 4, class: fpr128, preferred-register: '' }
- - { id: 5, class: fpr64, preferred-register: '' }
- - { id: 6, class: fpr128, preferred-register: '' }
- - { id: 7, class: fpr128, preferred-register: '' }
- - { id: 8, class: fpr128, preferred-register: '' }
-liveins:
- - { reg: '$x0', virtual-reg: '%0' }
- - { reg: '$x1', virtual-reg: '%1' }
-body: |
- bb.0.entry:
- liveins: $x0, $x1
-
- ; CHECK-LABEL: name: insert_vec_from_gpr64_zero_high
- ; CHECK: liveins: $x0, $x1
- ; CHECK-NEXT: {{ $}}
- ; CHECK-NEXT: [[PTR:%[0-9]+]]:gpr64common = COPY $x0
- ; CHECK-NEXT: [[VAL:%[0-9]+]]:gpr64common = COPY $x1
- ; CHECK-NEXT: [[GPR:%[0-9]+]]:gpr64 = COPY [[VAL]]
- ; CHECK-NEXT: [[FMOV:%[0-9]+]]:fpr64 = FMOVXDr killed [[GPR]]
- ; CHECK-NEXT: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_LOW:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[FMOV]], %subreg.dsub
- ; CHECK-NEXT: [[MOVID:%[0-9]+]]:fpr64 = MOVID 0
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_ZERO:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], killed [[MOVID]], %subreg.dsub
- ; CHECK-NEXT: STRQui killed [[INSERT_LOW]], [[PTR]], 0 :: (store (s128) into %ir.dst, align 8)
- ; CHECK-NEXT: RET_ReallyLR
- %0:gpr64common = COPY $x0
- %1:gpr64common = COPY $x1
- %2:fpr64 = COPY %1
- %4:fpr128 = IMPLICIT_DEF
- %3:fpr128 = INSERT_SUBREG %4, %2, %subreg.dsub
- %5:fpr64 = MOVID 0
- %7:fpr128 = IMPLICIT_DEF
- %6:fpr128 = INSERT_SUBREG %7, killed %5, %subreg.dsub
- %8:fpr128 = INSvi64lane %3, 1, killed %6, 0
- STRQui killed %8, %0, 0 :: (store (s128) into %ir.dst, align 8)
- RET_ReallyLR
-
...
diff --git a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
index de355fd..bd4cc62 100644
--- a/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
+++ b/llvm/test/CodeGen/AArch64/srem-seteq-illegal-types.ll
@@ -89,9 +89,9 @@
; CHECK-NEXT: add x8, x12, x8
; CHECK-NEXT: and v0.16b, v0.16b, v1.16b
; CHECK-NEXT: fmov d3, x8
-; CHECK-NEXT: mov w8, #3 // =0x3
+; CHECK-NEXT: adrp x8, .LCPI3_1
; CHECK-NEXT: cmeq v0.2d, v0.2d, v2.2d
-; CHECK-NEXT: fmov d2, x8
+; CHECK-NEXT: ldr q2, [x8, :lo12:.LCPI3_1]
; CHECK-NEXT: and v1.16b, v3.16b, v1.16b
; CHECK-NEXT: mvn v0.16b, v0.16b
; CHECK-NEXT: cmeq v1.2d, v1.2d, v2.2d
