llvm/test/tools/llvm-reduce/mir/reduce-instruction-flags.mir

# REQUIRES: amdgpu-registered-target
# RUN: llvm-reduce -abort-on-invalid-reduction -simplify-mir --delta-passes=instruction-flags -mtriple=amdgcn-amd-amdhsa --test FileCheck --test-arg --check-prefix=CHECK-INTERESTINGNESS --test-arg %s --test-arg --input-file %s -o %t 2> %t.log
# RUN: FileCheck --check-prefix=RESULT %s < %t

# CHECK-INTERESTINGNESS: V_ADD_F32
# CHECK-INTERESTINGNESS: nnan nofpexcept V_MUL_F32

# CHECK-INTERESTINGNESS-COUNT-11: V_MOV_B32


# RESULT: %{{[0-9]+}}:vgpr_32 = V_ADD_F32_e32 %{{[0-9]+}}, %{{[0-9]+}}, implicit $mode, implicit $exec
# RESULT: %{{[0-9]+}}:vgpr_32 = nnan nofpexcept V_MUL_F32_e32 0, %{{[0-9]+}}, implicit $mode, implicit $exec
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32
# RESULT: %{{[0-9]+}}:vgpr_32 = V_MOV_B32_e32

---
name: func
tracksRegLiveness: true
body:             |
  bb.0:
    liveins: $vgpr0, $vgpr1

    S_WAITCNT 0
    %0:vgpr_32 = COPY $vgpr0
    %1:vgpr_32 = COPY $vgpr1
    %2:vgpr_32 = nofpexcept V_ADD_F32_e32 %0, %1, implicit $mode, implicit $exec
    %3:vgpr_32 = nnan nofpexcept V_MUL_F32_e32 0, %2, implicit $mode, implicit $exec
    %4:vgpr_32 = nsz V_MUL_F32_e32 0, %3, implicit $mode, implicit $exec

    %5:vgpr_32 = nnan V_MOV_B32_e32 0, implicit $exec
    %6:vgpr_32 = ninf V_MOV_B32_e32 0, implicit $exec
    %7:vgpr_32 = nsz V_MOV_B32_e32 0, implicit $exec
    %8:vgpr_32 = arcp V_MOV_B32_e32 0, implicit $exec
    %9:vgpr_32 = contract V_MOV_B32_e32 0, implicit $exec
    %10:vgpr_32 = afn V_MOV_B32_e32 0, implicit $exec
    %11:vgpr_32 = reassoc V_MOV_B32_e32 0, implicit $exec
    %12:vgpr_32 = nuw V_MOV_B32_e32 0, implicit $exec
    %13:vgpr_32 = nsw V_MOV_B32_e32 0, implicit $exec
    %14:vgpr_32 = exact V_MOV_B32_e32 0, implicit $exec
    %15:vgpr_32 = nofpexcept V_MOV_B32_e32 0, implicit $exec
    S_NOP 0, implicit %3, implicit %4, implicit %5, implicit %6, implicit %7
    S_NOP 0, implicit %8, implicit %9, implicit %10, implicit %11, implicit %12
    S_ENDPGM 0, implicit %13, implicit %14, implicit %15
...