llvm/test/Transforms/InstCombine/get_active_lane_mask.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
; RUN: opt < %s -passes=instcombine -S | FileCheck %s

define <vscale x 4 x i1> @rewrite_range_nxv4i1() {
; CHECK-LABEL: define <vscale x 4 x i1> @rewrite_range_nxv4i1() {
; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 3)
; CHECK-NEXT:    ret <vscale x 4 x i1> [[MASK]]
;
  %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 1, i32 4)
  ret <vscale x 4 x i1> %mask
}

define <vscale x 16 x i1> @rewrite_range_nxv16i1() {
; CHECK-LABEL: define <vscale x 16 x i1> @rewrite_range_nxv16i1() {
; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 7)
; CHECK-NEXT:    ret <vscale x 16 x i1> [[MASK]]
;
  %mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 123123, i64 123130)
  ret <vscale x 16 x i1> %mask
}

define <vscale x 16 x i1> @rewrite_range_nxv16i1_i128() {
; CHECK-LABEL: define <vscale x 16 x i1> @rewrite_range_nxv16i1_i128() {
; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i128(i128 0, i128 10)
; CHECK-NEXT:    ret <vscale x 16 x i1> [[MASK]]
;
  %mask = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i128(i128 18446744073709551616, i128 18446744073709551626)
  ret <vscale x 16 x i1> %mask
}

define <vscale x 4 x i1> @bail_lhs_is_zero() {
; CHECK-LABEL: define <vscale x 4 x i1> @bail_lhs_is_zero() {
; CHECK-NEXT:    [[MASK:%.*]] = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
; CHECK-NEXT:    ret <vscale x 4 x i1> [[MASK]]
;
  %mask = call <vscale x 4 x i1> @llvm.get.active.lane.mask.nxv4i1.i32(i32 0, i32 4)
  ret <vscale x 4 x i1> %mask
}