llvm/test/CodeGen/RISCV/xmips-exectl.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=riscv64 -mcpu=mips-p8700 -O3  -verify-machineinstrs < %s \
; RUN:   | FileCheck -check-prefix=MIPS %s

target datalayout = "e-m:e-p:32:32-i64:64-n32-S128"

define void @test_mips_pause() {
; MIPS-LABEL: test_mips_pause:
; MIPS:       # %bb.0: # %entry
; MIPS-NEXT:    mips.pause
; MIPS-NEXT:    ret
entry:
  tail call void @llvm.riscv.mips.pause()
  ret void
}

define void @test_mips_ehb() {
; MIPS-LABEL: test_mips_ehb:
; MIPS:       # %bb.0: # %entry
; MIPS-NEXT:    mips.ehb
; MIPS-NEXT:    ret
entry:
  tail call void @llvm.riscv.mips.ehb()
  ret void
}

define void @test_mips_ihb() {
; MIPS-LABEL: test_mips_ihb:
; MIPS:       # %bb.0: # %entry
; MIPS-NEXT:    mips.ihb
; MIPS-NEXT:    ret
entry:
  tail call void @llvm.riscv.mips.ihb()
  ret void
}