llvm/test/CodeGen/RISCV/rvv/incorrect-extract-subvector-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=riscv64 -mattr=+zve64f,+zvl512b < %s | FileCheck %s

; Previously, an incorrect (extract_subvector (extract_subvector X, C), 0) DAG combine crashed
; this snippet.

define <8 x i16> @gsm_encode(ptr %p) {
; CHECK-LABEL: gsm_encode:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vsetivli zero, 19, e16, m1, ta, ma
; CHECK-NEXT:    vle16.v v8, (a0)
; CHECK-NEXT:    vslidedown.vi v9, v8, 12
; CHECK-NEXT:    vmv.x.s a0, v9
; CHECK-NEXT:    vsetivli zero, 8, e16, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v9, -1
; CHECK-NEXT:    vsetivli zero, 1, e16, m1, ta, ma
; CHECK-NEXT:    vslidedown.vi v8, v8, 9
; CHECK-NEXT:    vmv.x.s a1, v8
; CHECK-NEXT:    vsetivli zero, 8, e16, mf4, ta, ma
; CHECK-NEXT:    vmv.v.i v8, 0
; CHECK-NEXT:    vslide1down.vx v9, v9, zero
; CHECK-NEXT:    vslide1down.vx v8, v8, zero
; CHECK-NEXT:    vslide1down.vx v8, v8, zero
; CHECK-NEXT:    vslide1down.vx v8, v8, zero
; CHECK-NEXT:    vslide1down.vx v8, v8, zero
; CHECK-NEXT:    vslide1down.vx v8, v8, a1
; CHECK-NEXT:    vslide1down.vx v8, v8, a0
; CHECK-NEXT:    vslidedown.vi v8, v8, 1
; CHECK-NEXT:    vand.vv v8, v8, v9
; CHECK-NEXT:    ret
entry:
  %0 = load <19 x i16>, ptr %p, align 2
  %1 = shufflevector <19 x i16> zeroinitializer, <19 x i16> %0, <9 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 28, i32 31, i32 poison, i32 poison>
  %2 = shufflevector <9 x i16> %1, <9 x i16> zeroinitializer, <8 x i32> <i32 0, i32 1, i32 2, i32 3, i32 4, i32 5, i32 6, i32 15>
  ret <8 x i16> %2
}