llvm/test/CodeGen/LoongArch/lsx/ir-instruction/orn.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc --mtriple=loongarch32 --mattr=+32s,+lsx < %s | FileCheck %s
; RUN: llc --mtriple=loongarch64 --mattr=+lsx < %s | FileCheck %s

define void @orn_v16i8(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: orn_v16i8:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vorn.v $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <16 x i8>, ptr %a0
  %v1 = load <16 x i8>, ptr %a1
  %v2 = xor <16 x i8> %v1, <i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1, i8 -1>
  %v3 = or <16 x i8> %v0, %v2
  store <16 x i8> %v3, ptr %res
  ret void
}

define void @orn_v8i16(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: orn_v8i16:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vorn.v $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <8 x i16>, ptr %a0
  %v1 = load <8 x i16>, ptr %a1
  %v2 = xor <8 x i16> %v1, <i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1, i16 -1>
  %v3 = or <8 x i16> %v0, %v2
  store <8 x i16> %v3, ptr %res
  ret void
}

define void @orn_v4i32(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: orn_v4i32:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vorn.v $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <4 x i32>, ptr %a0
  %v1 = load <4 x i32>, ptr %a1
  %v2 = xor <4 x i32> %v1, <i32 -1, i32 -1, i32 -1, i32 -1>
  %v3 = or <4 x i32> %v0, %v2
  store <4 x i32> %v3, ptr %res
  ret void
}

define void @orn_v2i64(ptr %res, ptr %a0, ptr %a1) nounwind {
; CHECK-LABEL: orn_v2i64:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    vld $vr0, $a1, 0
; CHECK-NEXT:    vld $vr1, $a2, 0
; CHECK-NEXT:    vorn.v $vr0, $vr0, $vr1
; CHECK-NEXT:    vst $vr0, $a0, 0
; CHECK-NEXT:    ret
entry:
  %v0 = load <2 x i64>, ptr %a0
  %v1 = load <2 x i64>, ptr %a1
  %v2 = xor <2 x i64> %v1, <i64 -1, i64 -1>
  %v3 = or <2 x i64> %v0, %v2
  store <2 x i64> %v3, ptr %res
  ret void
}