commit 8e57689c34f0b0af70f9aaf009c3be0e85d90dda
author Daniel Henrique Barboza <dbarboza@ventanamicro.com> Wed Aug 06 13:08:25 2025 -0300
committer GitHub <noreply@github.com> Wed Aug 06 09:08:25 2025 -0700
tree 5c5aa7160f367ba997c11eb86944ee969818baed
parent 3686e5b52f2a02c1c19050479d1dd0fd9d1dd4f8

[RISCV] add load/store misched/PostRA subtarget features (#149409)

Some processors benefit more from store clustering than load clustering,
and vice-versa, depending on factors that are exclusive to each one
(e.g. macrofusions implemented).

Likewise, certain optimizations benefits more from misched clustering
than postRA clustering. Macrofusions are again an example: in a
processor with store pair macrofusions, like the veyron-v1, it is
observed that misched clustering increases the amount of macrofusions
more than postRA clustering. This of course isn't necessarily true for
other processors, but it shows that processors can benefit from a more
fine grained control of clustering mutations, and each one is able to do
it differently.

Add 4 new subtarget features that deprecates the existing
riscv-misched-load-store-clustering and
riscv-postmisched-load-store-clustering
options:

- disable-misched-load-clustering and disable-misched-store-clustering:
disable load/store clustering during misched;

- disable-postmisched-load-clustering and
disable-postmisched-store-clustering:
disable load/store clustering during PostRA.

Note that the new subtarget features disables specific stages of the
default
clustering settings. The default per se (load and store clustering for
both
misched and PostRA) is left untouched.

Disable all clustering but misched-store-clustering for the veyron-v1
processor
using the new features.