)]}'
{
  "commit": "8e57689c34f0b0af70f9aaf009c3be0e85d90dda",
  "tree": "5c5aa7160f367ba997c11eb86944ee969818baed",
  "parents": [
    "3686e5b52f2a02c1c19050479d1dd0fd9d1dd4f8"
  ],
  "author": {
    "name": "Daniel Henrique Barboza",
    "email": "dbarboza@ventanamicro.com",
    "time": "Wed Aug 06 13:08:25 2025 -0300"
  },
  "committer": {
    "name": "GitHub",
    "email": "noreply@github.com",
    "time": "Wed Aug 06 09:08:25 2025 -0700"
  },
  "message": "[RISCV] add load/store misched/PostRA subtarget features (#149409)\n\nSome processors benefit more from store clustering than load clustering,\nand vice-versa, depending on factors that are exclusive to each one\n(e.g. macrofusions implemented).\n\nLikewise, certain optimizations benefits more from misched clustering\nthan postRA clustering. Macrofusions are again an example: in a\nprocessor with store pair macrofusions, like the veyron-v1, it is\nobserved that misched clustering increases the amount of macrofusions\nmore than postRA clustering. This of course isn\u0027t necessarily true for\nother processors, but it shows that processors can benefit from a more\nfine grained control of clustering mutations, and each one is able to do\nit differently.\n\nAdd 4 new subtarget features that deprecates the existing\nriscv-misched-load-store-clustering and\nriscv-postmisched-load-store-clustering\noptions:\n\n- disable-misched-load-clustering and disable-misched-store-clustering:\ndisable load/store clustering during misched;\n\n- disable-postmisched-load-clustering and\ndisable-postmisched-store-clustering:\ndisable load/store clustering during PostRA.\n\nNote that the new subtarget features disables specific stages of the\ndefault\nclustering settings. The default per se (load and store clustering for\nboth\nmisched and PostRA) is left untouched.\n\nDisable all clustering but misched-store-clustering for the veyron-v1\nprocessor\nusing the new features.",
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