llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizer-combiner-zextload-from-and.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs -o - %s | FileCheck %s

# Post-legalizer should not generate illegal extending loads
---
name: zextload_from_inreg
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zextload_from_inreg
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s64) = G_LOAD [[COPY]](p1) :: (load (s64), addrspace 1)
    ; CHECK-NEXT: %k:_(s64) = G_CONSTANT i64 4294967295
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[LOAD]], %k
    ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[AND]](s64)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s64) = G_LOAD %0 :: (load (s64), align 8, addrspace 1)
    %k:_(s64) = G_CONSTANT i64 4294967295
    %2:_(s64) = G_AND %1, %k
    $vgpr0_vgpr1 = COPY %2
...

# Legal to fold into zextload
---
name: zext_inreg_8_zextload_s32
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_8_zextload_s32
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), align 4, addrspace 1)
    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 255
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

---
name: zext_inreg_7_zextload_s32
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_7_zextload_s32
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
    ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 127
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
    ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 127
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

---
name: zext_inreg_9_zextload_s32
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_9_zextload_s32
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s32) = G_LOAD [[COPY]](p1) :: (load (s32), addrspace 1)
    ; CHECK-NEXT: %k:_(s32) = G_CONSTANT i32 511
    ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[LOAD]], %k
    ; CHECK-NEXT: $vgpr0 = COPY [[AND]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 511
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

# Legal to fold into zextload
---
name: zext_inreg_16_zextload_s32
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_16_zextload_s32
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), align 4, addrspace 1)
    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (load (s32), align 4, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 65535
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

---
name: zext_inreg_8_zextload_s8
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_8_zextload_s8
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s8), addrspace 1)
    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (load (s8), align 1, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 255
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

---
name: zext_inreg_8_zextload_s8_volatile
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_8_zextload_s8_volatile
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s8), addrspace 1)
    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (volatile load (s8), align 1, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 255
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

---
name: zext_inreg_16_zextload_s16
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_16_zextload_s16
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (load (s16), addrspace 1)
    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (load (s16), align 2, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 65535
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...

---
name: zext_inreg_16_zextload_s16_volatile
tracksRegLiveness: true
legalized: true
body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: zext_inreg_16_zextload_s16_volatile
    ; CHECK: liveins: $vgpr0_vgpr1
    ; CHECK-NEXT: {{  $}}
    ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p1) = COPY $vgpr0_vgpr1
    ; CHECK-NEXT: [[ZEXTLOAD:%[0-9]+]]:_(s32) = G_ZEXTLOAD [[COPY]](p1) :: (volatile load (s16), addrspace 1)
    ; CHECK-NEXT: $vgpr0 = COPY [[ZEXTLOAD]](s32)
    %0:_(p1) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_LOAD %0 :: (volatile load (s16), align 2, addrspace 1)
    %k:_(s32) = G_CONSTANT i32 65535
    %2:_(s32) = G_AND %1, %k
    $vgpr0 = COPY %2
...