; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py | |
; RUN: llc -mtriple=riscv32 -mattr=+experimental-zbb -verify-machineinstrs < %s \ | |
; RUN: | FileCheck %s -check-prefix=RV32ZBB | |
declare i32 @llvm.riscv.orc.b.i32(i32) | |
define i32 @orcb(i32 %a) nounwind { | |
; RV32ZBB-LABEL: orcb: | |
; RV32ZBB: # %bb.0: | |
; RV32ZBB-NEXT: orc.b a0, a0 | |
; RV32ZBB-NEXT: ret | |
%tmp = call i32 @llvm.riscv.orc.b.i32(i32 %a) | |
ret i32 %tmp | |
} |