[InstCombine] Precommit tests for PR43580.
diff --git a/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll b/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll
index 40d58f3..dfc4160 100644
--- a/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll
+++ b/llvm/test/Transforms/InstCombine/trunc-binop-ext.ll
@@ -315,3 +315,88 @@
ret <2 x i16> %r
}
+; Test cases for PR43580
+define i8 @narrow_zext_ashr_keep_trunc(i8 %i1, i8 %i2) {
+; CHECK-LABEL: @narrow_zext_ashr_keep_trunc(
+; CHECK-NEXT: [[I1_EXT:%.*]] = sext i8 [[I1:%.*]] to i32
+; CHECK-NEXT: [[I2_EXT:%.*]] = sext i8 [[I2:%.*]] to i32
+; CHECK-NEXT: [[SUB:%.*]] = add nsw i32 [[I1_EXT]], [[I2_EXT]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i32 [[SUB]], 1
+; CHECK-NEXT: [[T:%.*]] = trunc i32 [[TMP1]] to i8
+; CHECK-NEXT: ret i8 [[T]]
+;
+ %i1.ext = sext i8 %i1 to i32
+ %i2.ext = sext i8 %i2 to i32
+ %sub = add nsw i32 %i1.ext, %i2.ext
+ %shift = ashr i32 %sub, 1
+ %t = trunc i32 %shift to i8
+ ret i8 %t
+}
+
+define i8 @narrow_zext_ashr_keep_trunc2(i9 %i1, i9 %i2) {
+; CHECK-LABEL: @narrow_zext_ashr_keep_trunc2(
+; CHECK-NEXT: [[I1_EXT1:%.*]] = zext i9 [[I1:%.*]] to i64
+; CHECK-NEXT: [[I2_EXT2:%.*]] = zext i9 [[I2:%.*]] to i64
+; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i64 [[I1_EXT1]], [[I2_EXT2]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[SUB]], 1
+; CHECK-NEXT: [[T:%.*]] = trunc i64 [[TMP1]] to i8
+; CHECK-NEXT: ret i8 [[T]]
+;
+ %i1.ext = sext i9 %i1 to i64
+ %i2.ext = sext i9 %i2 to i64
+ %sub = add nsw i64 %i1.ext, %i2.ext
+ %shift = ashr i64 %sub, 1
+ %t = trunc i64 %shift to i8
+ ret i8 %t
+}
+
+define i7 @narrow_zext_ashr_keep_trunc3(i8 %i1, i8 %i2) {
+; CHECK-LABEL: @narrow_zext_ashr_keep_trunc3(
+; CHECK-NEXT: [[I1_EXT1:%.*]] = zext i8 [[I1:%.*]] to i64
+; CHECK-NEXT: [[I2_EXT2:%.*]] = zext i8 [[I2:%.*]] to i64
+; CHECK-NEXT: [[SUB:%.*]] = add nuw nsw i64 [[I1_EXT1]], [[I2_EXT2]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i64 [[SUB]], 1
+; CHECK-NEXT: [[T:%.*]] = trunc i64 [[TMP1]] to i7
+; CHECK-NEXT: ret i7 [[T]]
+;
+ %i1.ext = sext i8 %i1 to i64
+ %i2.ext = sext i8 %i2 to i64
+ %sub = add nsw i64 %i1.ext, %i2.ext
+ %shift = ashr i64 %sub, 1
+ %t = trunc i64 %shift to i7
+ ret i7 %t
+}
+
+define <8 x i8> @narrow_zext_ashr_keep_trunc_vector(<8 x i8> %i1, <8 x i8> %i2) {
+; CHECK-LABEL: @narrow_zext_ashr_keep_trunc_vector(
+; CHECK-NEXT: [[I1_EXT:%.*]] = sext <8 x i8> [[I1:%.*]] to <8 x i32>
+; CHECK-NEXT: [[I2_EXT:%.*]] = sext <8 x i8> [[I2:%.*]] to <8 x i32>
+; CHECK-NEXT: [[SUB:%.*]] = add nsw <8 x i32> [[I1_EXT]], [[I2_EXT]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr <8 x i32> [[SUB]], <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+; CHECK-NEXT: [[T:%.*]] = trunc <8 x i32> [[TMP1]] to <8 x i8>
+; CHECK-NEXT: ret <8 x i8> [[T]]
+;
+ %i1.ext = sext <8 x i8> %i1 to <8 x i32>
+ %i2.ext = sext <8 x i8> %i2 to <8 x i32>
+ %sub = add nsw <8 x i32> %i1.ext, %i2.ext
+ %shift = ashr <8 x i32> %sub, <i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1, i32 1>
+ %t = trunc <8 x i32> %shift to <8 x i8>
+ ret <8 x i8> %t
+}
+
+define i8 @dont_narrow_zext_ashr_keep_trunc(i8 %i1, i8 %i2) {
+; CHECK-LABEL: @dont_narrow_zext_ashr_keep_trunc(
+; CHECK-NEXT: [[I1_EXT:%.*]] = sext i8 [[I1:%.*]] to i16
+; CHECK-NEXT: [[I2_EXT:%.*]] = sext i8 [[I2:%.*]] to i16
+; CHECK-NEXT: [[SUB:%.*]] = add nsw i16 [[I1_EXT]], [[I2_EXT]]
+; CHECK-NEXT: [[TMP1:%.*]] = lshr i16 [[SUB]], 1
+; CHECK-NEXT: [[T:%.*]] = trunc i16 [[TMP1]] to i8
+; CHECK-NEXT: ret i8 [[T]]
+;
+ %i1.ext = sext i8 %i1 to i16
+ %i2.ext = sext i8 %i2 to i16
+ %sub = add nsw i16 %i1.ext, %i2.ext
+ %shift = ashr i16 %sub, 1
+ %t = trunc i16 %shift to i8
+ ret i8 %t
+}
