| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5 | |
| ; RUN: opt -passes=loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC1 | |
| ; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=4 -S < %s | FileCheck %s --check-prefix=CHECK-VF4IC4 | |
| ; RUN: opt -passes=loop-vectorize -force-vector-interleave=4 -force-vector-width=1 -S < %s | FileCheck %s --check-prefix=CHECK-VF1IC4 | |
| ; About the truncated test cases, the range analysis of induction variable is | |
| ; used to ensure the induction variable is always greater than the sentinal | |
| ; value. The case is vectorizable if the truncated induction variable is | |
| ; monotonic increasing, and not equals to the sentinal. | |
| define i32 @select_icmp_const_truncated_iv_widened_exit(ptr %a, i32 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_icmp_const_truncated_iv_widened_exit( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[CMP_SGT:%.*]] = icmp sgt i32 [[N]], 0 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_SGT]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], splat (i64 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP4]]) | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP6]], -2147483648 | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP6]], i32 331 | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP7]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP8]], i32 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_icmp_const_truncated_iv_widened_exit( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[CMP_SGT:%.*]] = icmp sgt i32 [[N]], 0 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_SGT]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD4]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD5]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD6]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP10]], <4 x i32> [[TMP11]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[RDX_MINMAX]], <4 x i32> [[TMP12]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[RDX_MINMAX7]], <4 x i32> [[TMP13]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[RDX_MINMAX8]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP15]], -2147483648 | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP15]], i32 331 | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP16]], 3 | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP17]], i32 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_icmp_const_truncated_iv_widened_exit( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[CMP_SGT:%.*]] = icmp sgt i32 [[N]], 0 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_SGT]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF1IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = trunc i64 [[INDEX]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = add i32 [[TMP4]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i32 [[TMP4]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP9]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP10]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP11]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[TMP12]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = icmp sgt i64 [[TMP13]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP14]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = icmp sgt i64 [[TMP15]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp sgt i64 [[TMP16]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21]] = select i1 [[TMP17]], i32 [[TMP4]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22]] = select i1 [[TMP18]], i32 [[TMP6]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23]] = select i1 [[TMP19]], i32 [[TMP7]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], i32 [[TMP8]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP21]], i32 [[TMP22]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_MINMAX]], i32 [[TMP23]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_MINMAX4]], i32 [[TMP24]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[RDX_MINMAX5]], -2147483648 | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[RDX_MINMAX5]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP26:%.*]] = load i64, ptr [[ARRAYIDX]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i64 [[TMP26]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP27:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP27]], i32 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| entry: | |
| %cmp.sgt = icmp sgt i32 %n, 0 | |
| br i1 %cmp.sgt, label %for.body.preheader, label %exit | |
| for.body.preheader: | |
| %wide.trip.count = zext i32 %n to i64 | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %for.body.preheader ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ 331, %for.body.preheader ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %arrayidx, align 8 | |
| %cmp = icmp sgt i64 %0, 3 | |
| %1 = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %1, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, %wide.trip.count | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| %rdx.lcssa = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| ret i32 %rdx.lcssa | |
| } | |
| ; Without loop guard, the range analysis is also able to base on the constant | |
| ; trip count. | |
| define i32 @select_icmp_const_truncated_iv_const_exit(ptr %a) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_icmp_const_truncated_iv_const_exit( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], splat (i64 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20000 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP4]]) | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP6]], -2147483648 | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP6]], i32 331 | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_icmp_const_truncated_iv_const_exit( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i64, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i64>, ptr [[TMP3]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i64>, ptr [[TMP4]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i64>, ptr [[TMP5]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD4]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD5]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp sgt <4 x i64> [[WIDE_LOAD6]], splat (i64 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20000 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP10]], <4 x i32> [[TMP11]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[RDX_MINMAX]], <4 x i32> [[TMP12]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[RDX_MINMAX7]], <4 x i32> [[TMP13]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[RDX_MINMAX8]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP15]], -2147483648 | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP15]], i32 331 | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_icmp_const_truncated_iv_const_exit( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = trunc i64 [[INDEX]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = add i32 [[TMP4]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i32 [[TMP4]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds i64, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP9]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP10]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = load i64, ptr [[TMP11]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = load i64, ptr [[TMP12]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = icmp sgt i64 [[TMP13]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = icmp sgt i64 [[TMP14]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = icmp sgt i64 [[TMP15]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp sgt i64 [[TMP16]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21]] = select i1 [[TMP17]], i32 [[TMP4]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22]] = select i1 [[TMP18]], i32 [[TMP6]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23]] = select i1 [[TMP19]], i32 [[TMP7]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], i32 [[TMP8]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], 20000 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP21]], i32 [[TMP22]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_MINMAX]], i32 [[TMP23]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_MINMAX4]], i32 [[TMP24]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[RDX_MINMAX5]], -2147483648 | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[RDX_MINMAX5]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| entry: | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds i64, ptr %a, i64 %iv | |
| %0 = load i64, ptr %arrayidx, align 8 | |
| %cmp = icmp sgt i64 %0, 3 | |
| %1 = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %1, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, 20000 | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| ret i32 %spec.select | |
| } | |
| ; Without loop guard, the maximum constant trip count that can be vectorized is | |
| ; the signed maximum value of reduction type. | |
| define i32 @select_fcmp_max_valid_const_ub(ptr %a) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_fcmp_max_valid_const_ub( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[TMP4]]) | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP6]], -2147483648 | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP6]], i32 -1 | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_fcmp_max_valid_const_ub( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ splat (i32 -2147483648), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP5]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD4]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD5]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD6]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP14]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[TMP10]], <4 x i32> [[TMP11]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[RDX_MINMAX]], <4 x i32> [[TMP12]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i32> @llvm.smax.v4i32(<4 x i32> [[RDX_MINMAX7]], <4 x i32> [[TMP13]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = call i32 @llvm.vector.reduce.smax.v4i32(<4 x i32> [[RDX_MINMAX8]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP15]], -2147483648 | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP15]], i32 -1 | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_fcmp_max_valid_const_ub( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ -2147483648, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = trunc i64 [[INDEX]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i32 [[TMP4]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = add i32 [[TMP4]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i32 [[TMP4]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = load float, ptr [[TMP9]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = load float, ptr [[TMP10]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = load float, ptr [[TMP11]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = load float, ptr [[TMP12]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = fcmp fast olt float [[TMP13]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = fcmp fast olt float [[TMP14]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = fcmp fast olt float [[TMP15]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = fcmp fast olt float [[TMP16]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21]] = select i1 [[TMP17]], i32 [[TMP4]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22]] = select i1 [[TMP18]], i32 [[TMP6]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23]] = select i1 [[TMP19]], i32 [[TMP7]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], i32 [[TMP8]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[TMP21]], i32 [[TMP22]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_MINMAX]], i32 [[TMP23]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i32 @llvm.smax.i32(i32 [[RDX_MINMAX4]], i32 [[TMP24]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[RDX_MINMAX5]], -2147483648 | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[RDX_MINMAX5]], i32 -1 | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| entry: | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ -1, %entry ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv | |
| %0 = load float, ptr %arrayidx, align 4 | |
| %cmp = fcmp fast olt float %0, 0.000000e+00 | |
| %1 = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %1, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, 2147483648 | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| ret i32 %spec.select | |
| } | |
| ; The construct that are introduced by IndVarSimplify is: | |
| ; %1 = trunc i64 %iv to i32 | |
| ; The loop exit condition is a constant that overflows signed i32, | |
| ; but not unsigned i32: | |
| ; %exitcond.not = icmp eq i64 %inc, 4294967294 | |
| ; Hence, we can vectorize with the unsigned variant of FindLastIV. | |
| define i32 @select_icmp_truncated_unsigned_iv_range(ptr %a) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_icmp_truncated_unsigned_iv_range( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 2147483646, i32 2147483647, i32 -2147483648, i32 -2147483647>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = add nuw i64 2147483646, [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP3]] = select <4 x i1> [[TMP2]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP4]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP3]]) | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP5]], 0 | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP5]], i32 331 | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_icmp_truncated_unsigned_iv_range( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP9:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP10:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP11:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 2147483646, i32 2147483647, i32 -2147483648, i32 -2147483647>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[OFFSET_IDX:%.*]] = add nuw i64 2147483646, [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[OFFSET_IDX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP9]] = select <4 x i1> [[TMP5]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP10]] = select <4 x i1> [[TMP6]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP11]] = select <4 x i1> [[TMP7]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP13]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[TMP9]], <4 x i32> [[TMP10]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[RDX_MINMAX]], <4 x i32> [[TMP11]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[RDX_MINMAX7]], <4 x i32> [[TMP12]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[RDX_MINMAX8]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[TMP14]], 0 | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[TMP14]], i32 331 | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_icmp_truncated_unsigned_iv_range( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP19:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 2147483646, [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[OFFSET_IDX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[OFFSET_IDX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = trunc i64 [[OFFSET_IDX]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i32 [[TMP3]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i32 [[TMP3]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i32 [[TMP3]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[OFFSET_IDX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP0]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP8]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = load i32, ptr [[TMP9]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = load i32, ptr [[TMP10]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp sgt i32 [[TMP11]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP12]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = icmp sgt i32 [[TMP13]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = icmp sgt i32 [[TMP14]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19]] = select i1 [[TMP15]], i32 [[TMP3]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP20]] = select i1 [[TMP16]], i32 [[TMP4]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP21]] = select i1 [[TMP17]], i32 [[TMP5]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22]] = select i1 [[TMP18]], i32 [[TMP6]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP23]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP19]], i32 [[TMP20]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i32 @llvm.umax.i32(i32 [[RDX_MINMAX]], i32 [[TMP21]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX6:%.*]] = call i32 @llvm.umax.i32(i32 [[RDX_MINMAX5]], i32 [[TMP22]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT_CMP:%.*]] = icmp ne i32 [[RDX_MINMAX6]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[RDX_SELECT_CMP]], i32 [[RDX_MINMAX6]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[RDX_SELECT]] | |
| ; | |
| entry: | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 2147483646, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %0 = load i32, ptr %arrayidx, align 4 | |
| %cmp = icmp sgt i32 %0, 3 | |
| %conv = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %conv, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, 4294967294 | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| ret i32 %spec.select | |
| } | |
| ; Negative tests | |
| ; This test can theoretically be vectorized as a FindLastIV reduction, but only | |
| ; with a runtime-check. It will vectorize as a generic FindLast reduction. | |
| ; | |
| ; For FindLastIV, the construct that are introduced by IndVarSimplify is: | |
| ; %1 = trunc i64 %iv to i32 | |
| ; However, the loop guard is an i64: | |
| ; %cmp.sgt = icmp sgt i64 %n, 0 | |
| ; We cannot guarantee that %iv won't overflow an i32 value (and hence hit the | |
| ; sentinel value), and need a runtime-check to vectorize this case. | |
| define i32 @select_icmp_const_truncated_iv_unwidened_exit(ptr %a, i64 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_icmp_const_truncated_iv_unwidened_exit( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[CMP_SGT:%.*]] = icmp sgt i64 [[N]], 0 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_SGT]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = freeze <4 x i1> [[TMP8]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP2]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP5]], <4 x i1> [[TMP4]], i32 331) | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP7]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV1:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP1]], i32 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[TMP7]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_icmp_const_truncated_iv_unwidened_exit( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[CMP_SGT:%.*]] = icmp sgt i64 [[N]], 0 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_SGT]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP29:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP33:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = freeze <4 x i1> [[TMP1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = freeze <4 x i1> [[TMP33]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = freeze <4 x i1> [[TMP10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP34:%.*]] = or <4 x i1> [[TMP2]], [[TMP13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP34]], [[TMP15]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP18]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP3]], <4 x i1> [[TMP13]], <4 x i1> [[TMP12]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP3]], <4 x i1> [[TMP15]], <4 x i1> [[TMP19]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP3]], <4 x i1> [[TMP17]], <4 x i1> [[TMP20]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP5]], <4 x i1> [[TMP4]], i32 331) | |
| ; CHECK-VF4IC4-NEXT: [[TMP30:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP25]], <4 x i1> [[TMP21]], i32 [[TMP7]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP31:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP26]], <4 x i1> [[TMP22]], i32 [[TMP30]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP32:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP27]], <4 x i1> [[TMP23]], i32 [[TMP31]]) | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP32]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP8]], 3 | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP9]], i32 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[TMP32]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_icmp_const_truncated_iv_unwidened_exit( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[CMP_SGT:%.*]] = icmp sgt i64 [[N]], 0 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_SGT]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[N_MOD_VF]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP35:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP36:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP37:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP38:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP31:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP32:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP33:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP34:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[IV]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[IV]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i32 [[TMP7]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i32 [[TMP7]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i32 [[TMP7]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = icmp sgt i32 [[TMP17]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP18]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = icmp sgt i32 [[TMP19]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP24:%.*]] = freeze i1 [[CMP]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = freeze i1 [[TMP21]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP27:%.*]] = freeze i1 [[TMP22]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = freeze i1 [[TMP23]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP46:%.*]] = or i1 [[TMP24]], [[TMP25]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = or i1 [[TMP46]], [[TMP27]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = or i1 [[TMP28]], [[TMP29]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP30]], i1 [[TMP24]], i1 [[TMP12]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP30]], i1 [[TMP25]], i1 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP30]], i1 [[TMP27]], i1 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP30]], i1 [[TMP29]], i1 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP30]], i32 [[TMP8]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP30]], i32 [[TMP9]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP30]], i32 [[TMP10]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP38]] = select i1 [[TMP30]], i32 [[TMP11]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP39:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP39]], label %[[MIDDLE_BLOCK:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP40:%.*]] = select i1 [[TMP31]], i32 [[TMP35]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: [[TMP41:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 [[TMP40]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP42:%.*]] = select i1 [[TMP33]], i32 [[TMP37]], i32 [[TMP41]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP43:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP42]] | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP43]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY1:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY1]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV1:%.*]] = phi i64 [ [[INC:%.*]], %[[FOR_BODY1]] ], [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[SPEC_SELECT:%.*]], %[[FOR_BODY1]] ], [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP44]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP45:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i32 [[TMP45]], i32 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[N]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP8:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY1]] ], [ [[TMP43]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| entry: | |
| %cmp.sgt = icmp sgt i64 %n, 0 | |
| br i1 %cmp.sgt, label %for.body, label %exit | |
| for.body: | |
| %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %0 = load i32, ptr %arrayidx, align 4 | |
| %cmp = icmp sgt i32 %0, 3 | |
| %1 = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %1, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, %n | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| %rdx.lcssa = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| ret i32 %rdx.lcssa | |
| } | |
| ; This test can theoretically be vectorized as a FindLastIV reduction, but only | |
| ; with a runtime-check. It will vectorize as a generic FindLast reduction. | |
| ; | |
| ; For FindLastIV, the construct that are introduced by IndVarSimplify is: | |
| ; %1 = trunc i64 %iv to i32 | |
| ; However, the loop guard is unsigned: | |
| ; %cmp.not = icmp eq i32 %n, 0 | |
| ; We cannot guarantee that %iv won't overflow an i32 value (and hence hit the | |
| ; sentinel value), and need a runtime-check to vectorize this case. | |
| define i32 @select_icmp_const_truncated_iv_unsigned_loop_guard(ptr %a, i32 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_icmp_const_truncated_iv_unsigned_loop_guard( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[N]], 0 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY_PREHEADER:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP2]] = or <4 x i1> [[VEC_PHI1]], [[TMP8]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3]] = select <4 x i1> [[TMP8]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP3]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP2]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = freeze i1 [[TMP9]] | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP7]], i32 [[TMP5]], i32 331 | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i32 [[TMP1]], i32 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_icmp_const_truncated_iv_unsigned_loop_guard( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[N]], 0 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY_PREHEADER:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP29:%.*]] = getelementptr inbounds i32, ptr [[TMP0]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP29]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP33:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP16]] = or <4 x i1> [[VEC_PHI4]], [[TMP1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20]] = or <4 x i1> [[VEC_PHI5]], [[TMP33]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21]] = or <4 x i1> [[VEC_PHI6]], [[TMP10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22]] = or <4 x i1> [[VEC_PHI7]], [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP1]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP33]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[TMP12]], <4 x i32> [[TMP13]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[RDX_MINMAX]], <4 x i32> [[TMP14]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[RDX_MINMAX11]], <4 x i32> [[TMP15]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4IC4-NEXT: [[BIN_RDX:%.*]] = or <4 x i1> [[TMP20]], [[TMP16]] | |
| ; CHECK-VF4IC4-NEXT: [[BIN_RDX13:%.*]] = or <4 x i1> [[TMP21]], [[BIN_RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[BIN_RDX14:%.*]] = or <4 x i1> [[TMP22]], [[BIN_RDX13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[BIN_RDX14]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = freeze i1 [[TMP18]] | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP19]], i32 [[TMP17]], i32 331 | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP8]], 3 | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i32 [[TMP9]], i32 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ], [ [[RDX_SELECT]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_icmp_const_truncated_iv_unsigned_loop_guard( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[N]], 0 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY_PREHEADER:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF1IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI4:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP28:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI5:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI6:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI7:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[IV]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[IV]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i32 [[TMP7]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i32 [[TMP7]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i32 [[TMP7]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP0]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = icmp sgt i32 [[TMP17]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP18]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = icmp sgt i32 [[TMP19]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP28]] = or i1 [[VEC_PHI4]], [[CMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP20]] = or i1 [[VEC_PHI5]], [[TMP21]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29]] = or i1 [[VEC_PHI6]], [[TMP22]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30]] = or i1 [[VEC_PHI7]], [[TMP23]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[CMP1]], i32 [[TMP7]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP21]], i32 [[TMP9]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP22]], i32 [[TMP10]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP23]], i32 [[TMP11]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP39:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP39]], label %[[MIDDLE_BLOCK:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP27]], i32 [[TMP24]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX8:%.*]] = call i32 @llvm.umax.i32(i32 [[RDX_MINMAX]], i32 [[TMP25]]) | |
| ; CHECK-VF1IC4-NEXT: [[TMP35:%.*]] = call i32 @llvm.umax.i32(i32 [[RDX_MINMAX8]], i32 [[TMP26]]) | |
| ; CHECK-VF1IC4-NEXT: [[BIN_RDX:%.*]] = or i1 [[TMP20]], [[TMP28]] | |
| ; CHECK-VF1IC4-NEXT: [[BIN_RDX10:%.*]] = or i1 [[TMP29]], [[BIN_RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[BIN_RDX11:%.*]] = or i1 [[TMP30]], [[BIN_RDX10]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = freeze i1 [[BIN_RDX11]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP40:%.*]] = select i1 [[TMP31]], i32 [[TMP35]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP40]], %[[MIDDLE_BLOCK]] ], [ 331, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY1:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY1]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP44:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP2:%.*]] = icmp sgt i32 [[TMP44]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP45:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP2]], i32 [[TMP45]], i32 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP10:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY1]] ], [ [[TMP40]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_LCSSA:%.*]] = phi i32 [ 331, %[[ENTRY]] ], [ [[SPEC_SELECT_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[RDX_LCSSA]] | |
| ; | |
| entry: | |
| %cmp.not = icmp eq i32 %n, 0 | |
| br i1 %cmp.not, label %exit, label %for.body.preheader | |
| for.body.preheader: | |
| %wide.trip.count = zext i32 %n to i64 | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %for.body.preheader ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ 331, %for.body.preheader ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %0 = load i32, ptr %arrayidx, align 4 | |
| %cmp1 = icmp sgt i32 %0, 3 | |
| %1 = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp1, i32 %1, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, %wide.trip.count | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| %rdx.lcssa = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| ret i32 %rdx.lcssa | |
| } | |
| ; This test cannot be vectorized, even with a runtime check. | |
| ; The construct that are introduced by IndVarSimplify is: | |
| ; %1 = trunc i64 %iv to i32 | |
| ; However, the loop exit condition is a constant that overflows i32: | |
| ; %exitcond.not = icmp eq i64 %inc, 9223372036854775806 | |
| ; Hence, the i32 will most certainly wrap and hit the sentinel value, and we | |
| ; cannot vectorize this case. | |
| define i32 @not_vectorized_select_icmp_truncated_iv_out_of_bound(ptr %a) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @not_vectorized_select_icmp_truncated_iv_out_of_bound( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 -2, i32 -1, i32 0, i32 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = add nuw i64 4294967294, [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = freeze <4 x i1> [[TMP1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP2]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 9223372032559808512 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP5]], <4 x i1> [[TMP4]], i32 331) | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[TMP7]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @not_vectorized_select_icmp_truncated_iv_out_of_bound( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP4:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 -2, i32 -1, i32 0, i32 1>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = add nuw i64 4294967294, [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP20]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = freeze <4 x i1> [[TMP1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = freeze <4 x i1> [[TMP9]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = freeze <4 x i1> [[TMP10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP29:%.*]] = or <4 x i1> [[TMP2]], [[TMP13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP29]], [[TMP15]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = or <4 x i1> [[TMP16]], [[TMP17]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP18]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP4]] = select i1 [[TMP3]], <4 x i1> [[TMP2]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP3]], <4 x i1> [[TMP13]], <4 x i1> [[TMP8]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP3]], <4 x i1> [[TMP15]], <4 x i1> [[TMP12]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP3]], <4 x i1> [[TMP17]], <4 x i1> [[TMP19]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP3]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP3]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 9223372032559808512 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP5]], <4 x i1> [[TMP4]], i32 331) | |
| ; CHECK-VF4IC4-NEXT: [[TMP30:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP25]], <4 x i1> [[TMP21]], i32 [[TMP7]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP31:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP26]], <4 x i1> [[TMP22]], i32 [[TMP30]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP32:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP27]], <4 x i1> [[TMP23]], i32 [[TMP31]]) | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[TMP32]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @not_vectorized_select_icmp_truncated_iv_out_of_bound( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[FOR_BODY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 331, %[[FOR_BODY]] ], [ [[TMP35:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 331, %[[FOR_BODY]] ], [ [[TMP36:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 331, %[[FOR_BODY]] ], [ [[TMP37:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 331, %[[FOR_BODY]] ], [ [[TMP38:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP31:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP32:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP33:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP34:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = add i64 4294967294, [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[IV]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[IV]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i32 [[TMP7]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i32 [[TMP7]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i32 [[TMP7]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = icmp sgt i32 [[TMP17]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP18]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = icmp sgt i32 [[TMP19]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP24:%.*]] = freeze i1 [[CMP]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = freeze i1 [[TMP21]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP27:%.*]] = freeze i1 [[TMP22]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = freeze i1 [[TMP23]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP43:%.*]] = or i1 [[TMP24]], [[TMP25]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = or i1 [[TMP43]], [[TMP27]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = or i1 [[TMP28]], [[TMP29]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP30]], i1 [[TMP24]], i1 [[TMP12]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP30]], i1 [[TMP25]], i1 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP30]], i1 [[TMP27]], i1 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP30]], i1 [[TMP29]], i1 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP30]], i32 [[TMP8]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP30]], i32 [[TMP9]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP30]], i32 [[TMP10]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP38]] = select i1 [[TMP30]], i32 [[TMP11]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP39:%.*]] = icmp eq i64 [[INDEX_NEXT]], 9223372032559808512 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP39]], label %[[EXIT:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP40:%.*]] = select i1 [[TMP31]], i32 [[TMP35]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: [[TMP41:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 [[TMP40]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP42:%.*]] = select i1 [[TMP33]], i32 [[TMP37]], i32 [[TMP41]] | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP42]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT1:.*]] | |
| ; CHECK-VF1IC4: [[EXIT1]]: | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[SPEC_SELECT_LCSSA]] | |
| ; | |
| entry: | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 4294967294, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ 331, %entry ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %0 = load i32, ptr %arrayidx, align 4 | |
| %cmp = icmp sgt i32 %0, 3 | |
| %conv = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %conv, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, 9223372036854775806 | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| ret i32 %spec.select | |
| } | |
| ; Forbidding vectorization of the FindLastIV pattern involving a truncated | |
| ; induction variable in the absence of any loop guard. | |
| define i32 @not_vectorized_select_iv_icmp_no_guard(ptr %a, ptr %b, i32 %start, i32 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @not_vectorized_select_iv_icmp_no_guard( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[START:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[START]], i64 0 | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP12:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP6]], <4 x i1> [[TMP5]], i32 [[START]]) | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[COND:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP]], i32 [[TMP2]], i32 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i32 [ [[COND]], %[[FOR_BODY]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[COND_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @not_vectorized_select_iv_icmp_no_guard( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[START:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[START]], i64 0 | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP31:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP23:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP32:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP32]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP33:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP38:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP33]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, ptr [[TMP38]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD8]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], [[WIDE_LOAD9]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], [[WIDE_LOAD10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = freeze <4 x i1> [[TMP14]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21:%.*]] = freeze <4 x i1> [[TMP15]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP39:%.*]] = or <4 x i1> [[TMP3]], [[TMP17]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = or <4 x i1> [[TMP39]], [[TMP19]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP20]], [[TMP21]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP22]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x i1> [[TMP17]], <4 x i1> [[TMP12]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x i1> [[TMP19]], <4 x i1> [[TMP16]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP4]], <4 x i1> [[TMP21]], <4 x i1> [[TMP23]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP4]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP30]] = select i1 [[TMP4]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP31]] = select i1 [[TMP4]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP6]], <4 x i1> [[TMP5]], i32 [[START]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP35:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP29]], <4 x i1> [[TMP25]], i32 [[TMP9]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP36:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP30]], <4 x i1> [[TMP26]], i32 [[TMP35]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP37:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP31]], <4 x i1> [[TMP27]], i32 [[TMP36]]) | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP37]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[COND:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP]], i32 [[TMP2]], i32 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i32 [ [[COND]], %[[FOR_BODY]] ], [ [[TMP37]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[COND_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @not_vectorized_select_iv_icmp_no_guard( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i32 [[START:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP43:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP44:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP45:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP46:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP39:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP40:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP41:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP42:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[IV]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[IV]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i32 [[TMP7]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i32 [[TMP7]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i32 [[TMP7]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i32 [[TMP7]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP21]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP22]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP23]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = icmp sgt i32 [[TMP17]], [[TMP25]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = icmp sgt i32 [[TMP18]], [[TMP26]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = icmp sgt i32 [[TMP19]], [[TMP27]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP32:%.*]] = freeze i1 [[CMP]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP33:%.*]] = freeze i1 [[TMP29]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP35:%.*]] = freeze i1 [[TMP30]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP37:%.*]] = freeze i1 [[TMP31]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP55:%.*]] = or i1 [[TMP32]], [[TMP33]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP36:%.*]] = or i1 [[TMP55]], [[TMP35]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP38]], i1 [[TMP32]], i1 [[TMP12]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP38]], i1 [[TMP33]], i1 [[TMP16]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP41]] = select i1 [[TMP38]], i1 [[TMP35]], i1 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP42]] = select i1 [[TMP38]], i1 [[TMP37]], i1 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP43]] = select i1 [[TMP38]], i32 [[TMP8]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP44]] = select i1 [[TMP38]], i32 [[TMP9]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP45]] = select i1 [[TMP38]], i32 [[TMP10]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP46]] = select i1 [[TMP38]], i32 [[TMP11]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP47:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP47]], label %[[MIDDLE_BLOCK:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP48:%.*]] = select i1 [[TMP39]], i32 [[TMP43]], i32 [[START]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP49:%.*]] = select i1 [[TMP40]], i32 [[TMP44]], i32 [[TMP48]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP50:%.*]] = select i1 [[TMP41]], i32 [[TMP45]], i32 [[TMP49]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP51:%.*]] = select i1 [[TMP42]], i32 [[TMP46]], i32 [[TMP50]] | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP51]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY1:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY1]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[COND:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP52:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP53:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP1:%.*]] = icmp sgt i32 [[TMP52]], [[TMP53]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP54:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP1]], i32 [[TMP54]], i32 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP13:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i32 [ [[COND]], %[[FOR_BODY1]] ], [ [[TMP51]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[COND_LCSSA]] | |
| ; | |
| entry: | |
| %wide.trip.count = zext i32 %n to i64 | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ %start, %entry ], [ %cond, %for.body ] | |
| %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %0 = load i32, ptr %arrayidx, align 4 | |
| %arrayidx2 = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %1 = load i32, ptr %arrayidx2, align 4 | |
| %cmp = icmp sgt i32 %0, %1 | |
| %2 = trunc i64 %iv to i32 | |
| %cond = select i1 %cmp, i32 %2, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, %wide.trip.count | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| ret i32 %cond | |
| } | |
| ; Without loop guard, when the constant trip count exceeds the maximum signed | |
| ; value of the reduction type, truncation may cause overflow. Therefore, | |
| ; vectorizer is unable to guarantee that the induction variable is monotonic | |
| ; increasing. | |
| define i32 @not_vectorized_select_fcmp_invalid_const_ub(ptr %a) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @not_vectorized_select_fcmp_invalid_const_ub( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP3:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: [[TMP2]] = or <4 x i1> [[VEC_PHI1]], [[TMP8]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3]] = select <4 x i1> [[TMP8]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[TMP3]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP2]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = freeze i1 [[TMP9]] | |
| ; CHECK-VF4IC1-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP7]], i32 [[TMP5]], i32 -1 | |
| ; CHECK-VF4IC1-NEXT: br label %[[SCALAR_PH:.*]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV1:%.*]] = phi i64 [ 2147483648, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = fcmp fast olt float [[TMP0]], 0.000000e+00 | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP1]], i32 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], 2147483649 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[SPEC_SELECT_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @not_vectorized_select_fcmp_invalid_const_ub( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP16:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI5:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI6:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI7:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i32> [[STEP_ADD]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i32> [[STEP_ADD_2]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[ARRAYIDX]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds float, ptr [[ARRAYIDX]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP29:%.*]] = getelementptr inbounds float, ptr [[ARRAYIDX]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP24]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP28]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP29]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD4]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD5]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = fcmp fast olt <4 x float> [[WIDE_LOAD6]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP16]] = or <4 x i1> [[VEC_PHI4]], [[TMP8]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20]] = or <4 x i1> [[VEC_PHI5]], [[TMP9]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21]] = or <4 x i1> [[VEC_PHI6]], [[TMP10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22]] = or <4 x i1> [[VEC_PHI7]], [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i32> [[VEC_IND]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i32> [[STEP_ADD]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i32> [[STEP_ADD_2]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i32> [[STEP_ADD_3]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD_3]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[TMP12]], <4 x i32> [[TMP13]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX11:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[RDX_MINMAX]], <4 x i32> [[TMP14]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX12:%.*]] = call <4 x i32> @llvm.umax.v4i32(<4 x i32> [[RDX_MINMAX11]], <4 x i32> [[TMP15]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = call i32 @llvm.vector.reduce.umax.v4i32(<4 x i32> [[RDX_MINMAX12]]) | |
| ; CHECK-VF4IC4-NEXT: [[BIN_RDX:%.*]] = or <4 x i1> [[TMP20]], [[TMP16]] | |
| ; CHECK-VF4IC4-NEXT: [[BIN_RDX13:%.*]] = or <4 x i1> [[TMP21]], [[BIN_RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[BIN_RDX14:%.*]] = or <4 x i1> [[TMP22]], [[BIN_RDX13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[BIN_RDX14]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = freeze i1 [[TMP18]] | |
| ; CHECK-VF4IC4-NEXT: [[RDX_SELECT:%.*]] = select i1 [[TMP19]], i32 [[TMP17]], i32 -1 | |
| ; CHECK-VF4IC4-NEXT: br label %[[SCALAR_PH:.*]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV1:%.*]] = phi i64 [ 2147483648, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[RDX_SELECT]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = fcmp fast olt float [[TMP0]], 0.000000e+00 | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP]], i32 [[TMP1]], i32 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], 2147483649 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP15:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[SPEC_SELECT_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @not_vectorized_select_fcmp_invalid_const_ub( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*:]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[FOR_BODY]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 0, %[[FOR_BODY]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 0, %[[FOR_BODY]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 0, %[[FOR_BODY]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 0, %[[FOR_BODY]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI4:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP28:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI5:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP20:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI6:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI7:%.*]] = phi i1 [ false, %[[FOR_BODY]] ], [ [[TMP30:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[IV]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[IV]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i32 [[TMP7]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i32 [[TMP7]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i32 [[TMP7]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load float, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load float, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load float, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load float, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = fcmp fast olt float [[TMP0]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = fcmp fast olt float [[TMP17]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = fcmp fast olt float [[TMP18]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = fcmp fast olt float [[TMP19]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP28]] = or i1 [[VEC_PHI4]], [[CMP]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP20]] = or i1 [[VEC_PHI5]], [[TMP21]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29]] = or i1 [[VEC_PHI6]], [[TMP22]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30]] = or i1 [[VEC_PHI7]], [[TMP23]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[CMP]], i32 [[TMP7]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP21]], i32 [[TMP9]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP22]], i32 [[TMP10]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP23]], i32 [[TMP11]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP39:%.*]] = icmp eq i64 [[INDEX_NEXT]], 2147483648 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP39]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP14:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i32 @llvm.umax.i32(i32 [[TMP27]], i32 [[TMP24]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX8:%.*]] = call i32 @llvm.umax.i32(i32 [[RDX_MINMAX]], i32 [[TMP25]]) | |
| ; CHECK-VF1IC4-NEXT: [[TMP35:%.*]] = call i32 @llvm.umax.i32(i32 [[RDX_MINMAX8]], i32 [[TMP26]]) | |
| ; CHECK-VF1IC4-NEXT: [[BIN_RDX:%.*]] = or i1 [[TMP20]], [[TMP28]] | |
| ; CHECK-VF1IC4-NEXT: [[BIN_RDX10:%.*]] = or i1 [[TMP29]], [[BIN_RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[BIN_RDX11:%.*]] = or i1 [[TMP30]], [[BIN_RDX10]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = freeze i1 [[BIN_RDX11]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP40:%.*]] = select i1 [[TMP31]], i32 [[TMP35]], i32 -1 | |
| ; CHECK-VF1IC4-NEXT: br label %[[SCALAR_PH:.*]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY1:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY1]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV1:%.*]] = phi i64 [ 2147483648, %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[TMP40]], %[[SCALAR_PH]] ], [ [[SPEC_SELECT:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds float, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP44:%.*]] = load float, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP1:%.*]] = fcmp fast olt float [[TMP44]], 0.000000e+00 | |
| ; CHECK-VF1IC4-NEXT: [[TMP45:%.*]] = trunc i64 [[IV1]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT]] = select i1 [[CMP1]], i32 [[TMP45]], i32 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], 2147483649 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT:.*]], label %[[FOR_BODY1]], !llvm.loop [[LOOP15:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SPEC_SELECT_LCSSA:%.*]] = phi i32 [ [[SPEC_SELECT]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[SPEC_SELECT_LCSSA]] | |
| ; | |
| entry: | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %entry ], [ %inc, %for.body ] | |
| %rdx = phi i32 [ -1, %entry ], [ %spec.select, %for.body ] | |
| %arrayidx = getelementptr inbounds float, ptr %a, i64 %iv | |
| %0 = load float, ptr %arrayidx, align 4 | |
| %cmp = fcmp fast olt float %0, 0.000000e+00 | |
| %1 = trunc i64 %iv to i32 | |
| %spec.select = select i1 %cmp, i32 %1, i32 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, 2147483649 | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| ret i32 %spec.select | |
| } | |
| ; Even with loop guard protection, if the destination type of the truncation | |
| ; instruction is smaller than the trip count type before extension, overflow | |
| ; could still occur. | |
| define i16 @not_vectorized_select_iv_icmp_overflow_unwidened_tripcount(ptr %a, ptr %b, i16 %start, i32 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i16 @not_vectorized_select_iv_icmp_overflow_unwidened_tripcount( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i16 [[START:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N]], 0 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP9]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[START]], i64 0 | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i16> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ <i16 0, i16 1, i16 2, i16 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP3]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i16> [[VEC_IND]], <4 x i16> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[VEC_IND]], splat (i16 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP12:%.*]] = call i16 @llvm.experimental.vector.extract.last.active.v4i16(<4 x i16> [[TMP6]], <4 x i1> [[TMP5]], i16 [[START]]) | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP12]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[FOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i16 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[COND:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = trunc i64 [[IV1]] to i16 | |
| ; CHECK-VF4IC1-NEXT: [[COND]] = select i1 [[CMP3]], i16 [[TMP2]], i16 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[COND_LCSSA:%.*]] = phi i16 [ [[COND]], %[[FOR_BODY]] ], [ [[TMP12]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[RDX_0_LCSSA:%.*]] = phi i16 [ [[START]], %[[ENTRY]] ], [ [[COND_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i16 [[RDX_0_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i16 @not_vectorized_select_iv_icmp_overflow_unwidened_tripcount( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i16 [[START:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N]], 0 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP9]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i16> poison, i16 [[START]], i64 0 | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i16> [[BROADCAST_SPLATINSERT]], <4 x i16> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i16> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i16> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i16> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i16> [ [[BROADCAST_SPLAT]], %[[VECTOR_PH]] ], [ [[TMP31:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[LAST_ACTIVE_MASK:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP5:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP23:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i16> [ <i16 0, i16 1, i16 2, i16 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i16> [[VEC_IND]], splat (i16 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i16> [[STEP_ADD_2]], splat (i16 4) | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP32:%.*]] = getelementptr inbounds i32, ptr [[ARRAYIDX]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP24]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP28]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP32]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP33:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP34:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP38:%.*]] = getelementptr inbounds i32, ptr [[TMP10]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD1:%.*]] = load <4 x i32>, ptr [[TMP10]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD8:%.*]] = load <4 x i32>, ptr [[TMP33]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD9:%.*]] = load <4 x i32>, ptr [[TMP34]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD10:%.*]] = load <4 x i32>, ptr [[TMP38]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], [[WIDE_LOAD1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], [[WIDE_LOAD8]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], [[WIDE_LOAD9]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], [[WIDE_LOAD10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = freeze <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = freeze <4 x i1> [[TMP13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = freeze <4 x i1> [[TMP14]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21:%.*]] = freeze <4 x i1> [[TMP15]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP39:%.*]] = or <4 x i1> [[TMP3]], [[TMP17]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = or <4 x i1> [[TMP39]], [[TMP19]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22:%.*]] = or <4 x i1> [[TMP20]], [[TMP21]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP22]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP5]] = select i1 [[TMP4]], <4 x i1> [[TMP3]], <4 x i1> [[LAST_ACTIVE_MASK]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP4]], <4 x i1> [[TMP17]], <4 x i1> [[TMP12]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP4]], <4 x i1> [[TMP19]], <4 x i1> [[TMP16]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP4]], <4 x i1> [[TMP21]], <4 x i1> [[TMP23]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP4]], <4 x i16> [[VEC_IND]], <4 x i16> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP29]] = select i1 [[TMP4]], <4 x i16> [[STEP_ADD]], <4 x i16> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP30]] = select i1 [[TMP4]], <4 x i16> [[STEP_ADD_2]], <4 x i16> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP31]] = select i1 [[TMP4]], <4 x i16> [[STEP_ADD_3]], <4 x i16> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD_3]], splat (i16 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = call i16 @llvm.experimental.vector.extract.last.active.v4i16(<4 x i16> [[TMP6]], <4 x i1> [[TMP5]], i16 [[START]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP35:%.*]] = call i16 @llvm.experimental.vector.extract.last.active.v4i16(<4 x i16> [[TMP29]], <4 x i1> [[TMP25]], i16 [[TMP9]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP36:%.*]] = call i16 @llvm.experimental.vector.extract.last.active.v4i16(<4 x i16> [[TMP30]], <4 x i1> [[TMP26]], i16 [[TMP35]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP37:%.*]] = call i16 @llvm.experimental.vector.extract.last.active.v4i16(<4 x i16> [[TMP31]], <4 x i1> [[TMP27]], i16 [[TMP36]]) | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP37]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[FOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i16 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[COND:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = trunc i64 [[IV1]] to i16 | |
| ; CHECK-VF4IC4-NEXT: [[COND]] = select i1 [[CMP3]], i16 [[TMP2]], i16 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY]], !llvm.loop [[LOOP17:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[COND_LCSSA:%.*]] = phi i16 [ [[COND]], %[[FOR_BODY]] ], [ [[TMP37]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_0_LCSSA:%.*]] = phi i16 [ [[START]], %[[ENTRY]] ], [ [[COND_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i16 [[RDX_0_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i16 @not_vectorized_select_iv_icmp_overflow_unwidened_tripcount( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]], ptr [[B:%.*]], i16 [[START:%.*]], i32 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[CMP9:%.*]] = icmp sgt i32 [[N]], 0 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP9]], label %[[FOR_BODY_PREHEADER:.*]], label %[[EXIT:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY_PREHEADER]]: | |
| ; CHECK-VF1IC4-NEXT: [[WIDE_TRIP_COUNT:%.*]] = zext i32 [[N]] to i64 | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[WIDE_TRIP_COUNT]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i16 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP43:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i16 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP44:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i16 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP45:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i16 [ [[START]], %[[VECTOR_PH]] ], [ [[TMP46:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP39:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP40:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP41:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP42:%.*]], %[[FOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[IV]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[IV]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = trunc i64 [[IV]] to i16 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i16 [[TMP7]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i16 [[TMP7]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i16 [[TMP7]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i16 [[TMP7]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = load i32, ptr [[ARRAYIDX]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = load i32, ptr [[ARRAYIDX2]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = load i32, ptr [[TMP21]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP26:%.*]] = load i32, ptr [[TMP22]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP27:%.*]] = load i32, ptr [[TMP23]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP3:%.*]] = icmp sgt i32 [[TMP0]], [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = icmp sgt i32 [[TMP17]], [[TMP25]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = icmp sgt i32 [[TMP18]], [[TMP26]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = icmp sgt i32 [[TMP19]], [[TMP27]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP32:%.*]] = freeze i1 [[CMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP33:%.*]] = freeze i1 [[TMP29]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP35:%.*]] = freeze i1 [[TMP30]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP37:%.*]] = freeze i1 [[TMP31]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP55:%.*]] = or i1 [[TMP32]], [[TMP33]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP36:%.*]] = or i1 [[TMP55]], [[TMP35]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP38:%.*]] = or i1 [[TMP36]], [[TMP37]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP38]], i1 [[TMP32]], i1 [[TMP12]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP40]] = select i1 [[TMP38]], i1 [[TMP33]], i1 [[TMP16]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP41]] = select i1 [[TMP38]], i1 [[TMP35]], i1 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP42]] = select i1 [[TMP38]], i1 [[TMP37]], i1 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP43]] = select i1 [[TMP38]], i16 [[TMP8]], i16 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP44]] = select i1 [[TMP38]], i16 [[TMP9]], i16 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP45]] = select i1 [[TMP38]], i16 [[TMP10]], i16 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP46]] = select i1 [[TMP38]], i16 [[TMP11]], i16 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[IV]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP47:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP47]], label %[[MIDDLE_BLOCK:.*]], label %[[FOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP48:%.*]] = select i1 [[TMP39]], i16 [[TMP43]], i16 [[START]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP49:%.*]] = select i1 [[TMP40]], i16 [[TMP44]], i16 [[TMP48]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP50:%.*]] = select i1 [[TMP41]], i16 [[TMP45]], i16 [[TMP49]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP51:%.*]] = select i1 [[TMP42]], i16 [[TMP46]], i16 [[TMP50]] | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[WIDE_TRIP_COUNT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ [[TMP51]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[FOR_BODY_PREHEADER]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[FOR_BODY1:.*]] | |
| ; CHECK-VF1IC4: [[FOR_BODY1]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[INC:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i16 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[COND:%.*]], %[[FOR_BODY1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP52:%.*]] = load i32, ptr [[ARRAYIDX1]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i32, ptr [[B]], i64 [[IV1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP53:%.*]] = load i32, ptr [[ARRAYIDX3]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP52]], [[TMP53]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP54:%.*]] = trunc i64 [[IV1]] to i16 | |
| ; CHECK-VF1IC4-NEXT: [[COND]] = select i1 [[CMP4]], i16 [[TMP54]], i16 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[INC]] = add nuw nsw i64 [[IV1]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INC]], [[WIDE_TRIP_COUNT]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXITCOND_NOT]], label %[[EXIT_LOOPEXIT]], label %[[FOR_BODY1]], !llvm.loop [[LOOP17:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT_LOOPEXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[COND_LCSSA:%.*]] = phi i16 [ [[COND]], %[[FOR_BODY1]] ], [ [[TMP51]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[EXIT]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_0_LCSSA:%.*]] = phi i16 [ [[START]], %[[ENTRY]] ], [ [[COND_LCSSA]], %[[EXIT_LOOPEXIT]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i16 [[RDX_0_LCSSA]] | |
| ; | |
| entry: | |
| %cmp9 = icmp sgt i32 %n, 0 | |
| br i1 %cmp9, label %for.body.preheader, label %exit | |
| for.body.preheader: | |
| %wide.trip.count = zext i32 %n to i64 | |
| br label %for.body | |
| for.body: | |
| %iv = phi i64 [ 0, %for.body.preheader ], [ %inc, %for.body ] | |
| %rdx = phi i16 [ %start, %for.body.preheader ], [ %cond, %for.body ] | |
| %arrayidx = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %0 = load i32, ptr %arrayidx, align 4 | |
| %arrayidx2 = getelementptr inbounds i32, ptr %b, i64 %iv | |
| %1 = load i32, ptr %arrayidx2, align 4 | |
| %cmp3 = icmp sgt i32 %0, %1 | |
| %2 = trunc i64 %iv to i16 | |
| %cond = select i1 %cmp3, i16 %2, i16 %rdx | |
| %inc = add nuw nsw i64 %iv, 1 | |
| %exitcond.not = icmp eq i64 %inc, %wide.trip.count | |
| br i1 %exitcond.not, label %exit, label %for.body | |
| exit: | |
| %rdx.0.lcssa = phi i16 [ %start, %entry ], [ %cond, %for.body ] | |
| ret i16 %rdx.0.lcssa | |
| } | |
| ; Test that we don't incorrectly identify a truncated i1 IV as a FindFirstIV | |
| ; reduction. The truncated IV wraps (alternates 0, 1, 0, 1, ...). | |
| ; Test for https://github.com/llvm/llvm-project/issues/173459. | |
| define i1 @select_with_trunc_i1_iv(i64 %n, i64 %start) { | |
| ; CHECK-LABEL: define i1 @select_with_trunc_i1_iv( | |
| ; CHECK-SAME: i64 [[N:%.*]], i64 [[START:%.*]]) { | |
| ; CHECK-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK: [[LOOP]]: | |
| ; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[START]], %[[ENTRY]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[CTR:%.*]] = phi i64 [ 0, %[[ENTRY]] ], [ [[CTR_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[ACCUM:%.*]] = phi i1 [ false, %[[ENTRY]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV]], 0 | |
| ; CHECK-NEXT: [[TRUNC:%.*]] = trunc i64 [[CTR]] to i1 | |
| ; CHECK-NEXT: [[SEL]] = select i1 [[CMP]], i1 [[ACCUM]], i1 [[TRUNC]] | |
| ; CHECK-NEXT: [[CTR_NEXT]] = add i64 [[CTR]], 1 | |
| ; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 | |
| ; CHECK-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[N]], [[CTR]] | |
| ; CHECK-NEXT: br i1 [[EXIT_COND]], label %[[EXIT:.*]], label %[[LOOP]] | |
| ; CHECK: [[EXIT]]: | |
| ; CHECK-NEXT: [[SEL_LCSSA:%.*]] = phi i1 [ [[SEL]], %[[LOOP]] ] | |
| ; CHECK-NEXT: ret i1 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC1-LABEL: define i1 @select_with_trunc_i1_iv( | |
| ; CHECK-VF4IC1-SAME: i64 [[N:%.*]], i64 [[START:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = add i64 [[START]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[START]], i64 0 | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: [[INDUCTION:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3> | |
| ; CHECK-VF4IC1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4IC1: [[LOOP]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i1> [ <i1 false, i1 true, i1 false, i1 true>, %[[VECTOR_PH]] ], [ [[VEC_PHI]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[VEC_IND]], zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP4]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP2]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[VEC_PHI]], <4 x i1> [[VEC_IND1]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = call i1 @llvm.experimental.vector.extract.last.active.v4i1(<4 x i1> [[TMP7]], <4 x i1> [[TMP6]], i1 false) | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i1 [ [[TMP9]], %[[MIDDLE_BLOCK]] ], [ false, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[LOOP1:.*]] | |
| ; CHECK-VF4IC1: [[LOOP1]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF4IC1-NEXT: [[CTR:%.*]] = phi i64 [ [[BC_RESUME_VAL2]], %[[SCALAR_PH]] ], [ [[CTR_NEXT:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF4IC1-NEXT: [[ACCUM:%.*]] = phi i1 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV]], 0 | |
| ; CHECK-VF4IC1-NEXT: [[TRUNC:%.*]] = trunc i64 [[CTR]] to i1 | |
| ; CHECK-VF4IC1-NEXT: [[SEL]] = select i1 [[CMP]], i1 [[ACCUM]], i1 [[TRUNC]] | |
| ; CHECK-VF4IC1-NEXT: [[CTR_NEXT]] = add i64 [[CTR]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[N]], [[CTR]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP19:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SEL_LCSSA:%.*]] = phi i1 [ [[SEL]], %[[LOOP1]] ], [ [[TMP9]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i1 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i1 @select_with_trunc_i1_iv( | |
| ; CHECK-VF4IC4-SAME: i64 [[N:%.*]], i64 [[START:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = add i64 [[START]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[START]], i64 0 | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[INDUCTION:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], <i64 0, i64 1, i64 2, i64 3> | |
| ; CHECK-VF4IC4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4IC4: [[LOOP]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI4:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND1:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP20:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND4:%.*]] = phi <4 x i1> [ <i1 false, i1 true, i1 false, i1 true>, %[[VECTOR_PH]] ], [ [[VEC_IND4]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = icmp ne <4 x i64> [[VEC_IND]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = icmp ne <4 x i64> [[STEP_ADD]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = icmp ne <4 x i64> [[STEP_ADD_2]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp ne <4 x i64> [[STEP_ADD_3]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = freeze <4 x i1> [[TMP3]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = freeze <4 x i1> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = freeze <4 x i1> [[TMP18]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = freeze <4 x i1> [[TMP9]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = or <4 x i1> [[TMP4]], [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = or <4 x i1> [[TMP19]], [[TMP13]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = or <4 x i1> [[TMP14]], [[TMP15]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP16]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6]] = select i1 [[TMP5]], <4 x i1> [[TMP4]], <4 x i1> [[TMP2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP7]] = select i1 [[TMP5]], <4 x i1> [[TMP11]], <4 x i1> [[VEC_IND1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20]] = select i1 [[TMP5]], <4 x i1> [[TMP13]], <4 x i1> [[TMP10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP5]], <4 x i1> [[TMP15]], <4 x i1> [[TMP17]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI4]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP5]], <4 x i1> [[VEC_IND4]], <4 x i1> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP8]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP27:%.*]] = call i1 @llvm.experimental.vector.extract.last.active.v4i1(<4 x i1> [[TMP22]], <4 x i1> [[TMP6]], i1 false) | |
| ; CHECK-VF4IC4-NEXT: [[TMP28:%.*]] = call i1 @llvm.experimental.vector.extract.last.active.v4i1(<4 x i1> [[TMP23]], <4 x i1> [[TMP7]], i1 [[TMP27]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP29:%.*]] = call i1 @llvm.experimental.vector.extract.last.active.v4i1(<4 x i1> [[TMP24]], <4 x i1> [[TMP20]], i1 [[TMP28]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP30:%.*]] = call i1 @llvm.experimental.vector.extract.last.active.v4i1(<4 x i1> [[TMP25]], <4 x i1> [[TMP21]], i1 [[TMP29]]) | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL5:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i1 [ [[TMP30]], %[[MIDDLE_BLOCK]] ], [ false, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[LOOP1:.*]] | |
| ; CHECK-VF4IC4: [[LOOP1]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF4IC4-NEXT: [[CTR:%.*]] = phi i64 [ [[BC_RESUME_VAL5]], %[[SCALAR_PH]] ], [ [[CTR_NEXT:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF4IC4-NEXT: [[ACCUM:%.*]] = phi i1 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV]], 0 | |
| ; CHECK-VF4IC4-NEXT: [[TRUNC:%.*]] = trunc i64 [[CTR]] to i1 | |
| ; CHECK-VF4IC4-NEXT: [[SEL]] = select i1 [[CMP]], i1 [[ACCUM]], i1 [[TRUNC]] | |
| ; CHECK-VF4IC4-NEXT: [[CTR_NEXT]] = add i64 [[CTR]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[N]], [[CTR]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP19:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SEL_LCSSA:%.*]] = phi i1 [ [[SEL]], %[[LOOP1]] ], [ [[TMP30]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i1 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i1 @select_with_trunc_i1_iv( | |
| ; CHECK-VF1IC4-SAME: i64 [[N:%.*]], i64 [[START:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = add i64 [[START]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1IC4: [[LOOP]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP29:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP30:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP31:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP32:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP28:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[START]], [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = add i64 [[OFFSET_IDX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = trunc i64 [[INDEX]] to i1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i1 [[TMP9]], false | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i1 [[TMP9]], true | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = add i1 [[TMP9]], false | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = add i1 [[TMP9]], true | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = icmp ne i64 [[OFFSET_IDX]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp ne i64 [[TMP6]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = icmp ne i64 [[TMP7]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = icmp ne i64 [[TMP8]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = freeze i1 [[TMP14]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = freeze i1 [[TMP15]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = freeze i1 [[TMP16]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = freeze i1 [[TMP17]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP38:%.*]] = or i1 [[TMP18]], [[TMP19]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = or i1 [[TMP38]], [[TMP21]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24:%.*]] = or i1 [[TMP22]], [[TMP23]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP24]], i1 [[TMP18]], i1 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP24]], i1 [[TMP19]], i1 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP24]], i1 [[TMP21]], i1 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP28]] = select i1 [[TMP24]], i1 [[TMP23]], i1 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29]] = select i1 [[TMP24]], i1 [[TMP10]], i1 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30]] = select i1 [[TMP24]], i1 [[TMP11]], i1 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31]] = select i1 [[TMP24]], i1 [[TMP12]], i1 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP24]], i1 [[TMP13]], i1 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP33:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP33]], label %[[MIDDLE_BLOCK:.*]], label %[[LOOP]], !llvm.loop [[LOOP18:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP34:%.*]] = select i1 [[TMP25]], i1 [[TMP29]], i1 false | |
| ; CHECK-VF1IC4-NEXT: [[TMP35:%.*]] = select i1 [[TMP26]], i1 [[TMP30]], i1 [[TMP34]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP36:%.*]] = select i1 [[TMP27]], i1 [[TMP31]], i1 [[TMP35]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP37:%.*]] = select i1 [[TMP28]], i1 [[TMP32]], i1 [[TMP36]] | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[TMP1]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i1 [ [[TMP37]], %[[MIDDLE_BLOCK]] ], [ false, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[LOOP1:.*]] | |
| ; CHECK-VF1IC4: [[LOOP1]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[CTR:%.*]] = phi i64 [ [[BC_RESUME_VAL4]], %[[SCALAR_PH]] ], [ [[CTR_NEXT:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[ACCUM:%.*]] = phi i1 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP1]] ] | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp eq i64 [[IV]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TRUNC:%.*]] = trunc i64 [[CTR]] to i1 | |
| ; CHECK-VF1IC4-NEXT: [[SEL]] = select i1 [[CMP]], i1 [[ACCUM]], i1 [[TRUNC]] | |
| ; CHECK-VF1IC4-NEXT: [[CTR_NEXT]] = add i64 [[CTR]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[N]], [[CTR]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP1]], !llvm.loop [[LOOP19:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SEL_LCSSA:%.*]] = phi i1 [ [[SEL]], %[[LOOP1]] ], [ [[TMP37]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i1 [[SEL_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ %start, %entry ], [ %iv.next, %loop ] | |
| %ctr = phi i64 [ 0, %entry ], [ %ctr.next, %loop ] | |
| %accum = phi i1 [ false, %entry ], [ %sel, %loop ] | |
| %cmp = icmp eq i64 %iv, 0 | |
| %trunc = trunc i64 %ctr to i1 | |
| %sel = select i1 %cmp, i1 %accum, i1 %trunc | |
| %ctr.next = add i64 %ctr, 1 | |
| %iv.next = add i64 %iv, 1 | |
| %exit.cond = icmp eq i64 %n, %ctr | |
| br i1 %exit.cond, label %exit, label %loop | |
| exit: | |
| ret i1 %sel | |
| } | |
| ; The i64 induction is also widened for the store. | |
| define i32 @select_icmp_truncated_iv_also_widened(ptr noalias %a, ptr noalias %b, i64 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i32 @select_icmp_truncated_iv_also_widened( | |
| ; CHECK-VF4IC1-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP7:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND1:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT2:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = freeze <4 x i1> [[TMP2]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP8]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP6]] = select i1 [[TMP9]], <4 x i1> [[TMP8]], <4 x i1> [[TMP3]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP7]] = select i1 [[TMP9]], <4 x i32> [[VEC_IND1]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP4]], align 8 | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT2]] = add <4 x i32> [[VEC_IND1]], splat (i32 4) | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP7]], <4 x i1> [[TMP6]], i32 331) | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 331, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4IC1: [[LOOP]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[L:%.*]] = load i32, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[L]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[TRUNC:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF4IC1-NEXT: [[SEL]] = select i1 [[CMP]], i32 [[TRUNC]], i32 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: store i64 [[IV]], ptr [[GEP_B]], align 8 | |
| ; CHECK-VF4IC1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP21:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SEL_LCSSA:%.*]] = phi i32 [ [[SEL]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i32 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i32 @select_icmp_truncated_iv_also_widened( | |
| ; CHECK-VF4IC4-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i32> [ splat (i32 331), %[[VECTOR_PH]] ], [ [[TMP28:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP21:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP22:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP23:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TMP12:%.*]] = phi <4 x i1> [ zeroinitializer, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND4:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT11:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add nuw <4 x i64> [[VEC_IND]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add nuw <4 x i64> [[STEP_ADD]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add nuw <4 x i64> [[STEP_ADD_2]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD5:%.*]] = add <4 x i32> [[VEC_IND4]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_26:%.*]] = add <4 x i32> [[STEP_ADD5]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_37:%.*]] = add <4 x i32> [[STEP_ADD_26]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP1]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP2]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP3]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], splat (i32 3) | |
| ; CHECK-VF4IC4-NEXT: [[TMP29:%.*]] = freeze <4 x i1> [[TMP5]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP30:%.*]] = freeze <4 x i1> [[TMP6]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP32:%.*]] = freeze <4 x i1> [[TMP7]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = freeze <4 x i1> [[TMP8]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP31:%.*]] = or <4 x i1> [[TMP29]], [[TMP30]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP33:%.*]] = or <4 x i1> [[TMP31]], [[TMP32]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = or <4 x i1> [[TMP33]], [[TMP18]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP20:%.*]] = call i1 @llvm.vector.reduce.or.v4i1(<4 x i1> [[TMP19]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP21]] = select i1 [[TMP20]], <4 x i1> [[TMP29]], <4 x i1> [[TMP9]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP22]] = select i1 [[TMP20]], <4 x i1> [[TMP30]], <4 x i1> [[TMP10]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP23]] = select i1 [[TMP20]], <4 x i1> [[TMP32]], <4 x i1> [[TMP11]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], <4 x i1> [[TMP18]], <4 x i1> [[TMP12]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP25]] = select i1 [[TMP20]], <4 x i32> [[VEC_IND4]], <4 x i32> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP26]] = select i1 [[TMP20]], <4 x i32> [[STEP_ADD5]], <4 x i32> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP27]] = select i1 [[TMP20]], <4 x i32> [[STEP_ADD_26]], <4 x i32> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP28]] = select i1 [[TMP20]], <4 x i32> [[STEP_ADD_37]], <4 x i32> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14:%.*]] = getelementptr inbounds i64, ptr [[TMP13]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP15:%.*]] = getelementptr inbounds i64, ptr [[TMP13]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = getelementptr inbounds i64, ptr [[TMP13]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: store <4 x i64> [[VEC_IND]], ptr [[TMP13]], align 8 | |
| ; CHECK-VF4IC4-NEXT: store <4 x i64> [[STEP_ADD]], ptr [[TMP14]], align 8 | |
| ; CHECK-VF4IC4-NEXT: store <4 x i64> [[STEP_ADD_2]], ptr [[TMP15]], align 8 | |
| ; CHECK-VF4IC4-NEXT: store <4 x i64> [[STEP_ADD_3]], ptr [[TMP16]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add nuw nsw <4 x i64> [[STEP_ADD_3]], splat (i64 4) | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT11]] = add <4 x i32> [[STEP_ADD_37]], splat (i32 4) | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP17]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP34:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP25]], <4 x i1> [[TMP21]], i32 331) | |
| ; CHECK-VF4IC4-NEXT: [[TMP35:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP26]], <4 x i1> [[TMP22]], i32 [[TMP34]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP36:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP27]], <4 x i1> [[TMP23]], i32 [[TMP35]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP37:%.*]] = call i32 @llvm.experimental.vector.extract.last.active.v4i32(<4 x i32> [[TMP28]], <4 x i1> [[TMP24]], i32 [[TMP36]]) | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP37]], %[[MIDDLE_BLOCK]] ], [ 331, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4IC4: [[LOOP]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[L:%.*]] = load i32, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[L]], 3 | |
| ; CHECK-VF4IC4-NEXT: [[TRUNC:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF4IC4-NEXT: [[SEL]] = select i1 [[CMP]], i32 [[TRUNC]], i32 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: store i64 [[IV]], ptr [[GEP_B]], align 8 | |
| ; CHECK-VF4IC4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP21:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SEL_LCSSA:%.*]] = phi i32 [ [[SEL]], %[[LOOP]] ], [ [[TMP37]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i32 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i32 @select_icmp_truncated_iv_also_widened( | |
| ; CHECK-VF1IC4-SAME: ptr noalias [[A:%.*]], ptr noalias [[B:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP36:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP37:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP38:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i32 [ 331, %[[VECTOR_PH]] ], [ [[TMP39:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP32:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP33:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP34:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = phi i1 [ false, %[[VECTOR_PH]] ], [ [[TMP35:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = trunc i64 [[INDEX]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = add i32 [[TMP20]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP41:%.*]] = add i32 [[TMP20]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP42:%.*]] = add i32 [[TMP20]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP43:%.*]] = add i32 [[TMP20]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP6]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = load i32, ptr [[TMP7]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP8]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = icmp sgt i32 [[TMP9]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = icmp sgt i32 [[TMP10]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = icmp sgt i32 [[TMP11]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = icmp sgt i32 [[TMP12]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP44:%.*]] = freeze i1 [[TMP13]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP26:%.*]] = freeze i1 [[TMP14]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = freeze i1 [[TMP15]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = freeze i1 [[TMP16]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP49:%.*]] = or i1 [[TMP44]], [[TMP26]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = or i1 [[TMP49]], [[TMP28]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP31:%.*]] = or i1 [[TMP29]], [[TMP30]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP32]] = select i1 [[TMP31]], i1 [[TMP44]], i1 [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP33]] = select i1 [[TMP31]], i1 [[TMP26]], i1 [[TMP17]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP34]] = select i1 [[TMP31]], i1 [[TMP28]], i1 [[TMP18]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP35]] = select i1 [[TMP31]], i1 [[TMP30]], i1 [[TMP19]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP36]] = select i1 [[TMP31]], i32 [[TMP21]], i32 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP37]] = select i1 [[TMP31]], i32 [[TMP41]], i32 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP38]] = select i1 [[TMP31]], i32 [[TMP42]], i32 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP39]] = select i1 [[TMP31]], i32 [[TMP43]], i32 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP40:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP24:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: store i64 [[INDEX]], ptr [[TMP40]], align 8 | |
| ; CHECK-VF1IC4-NEXT: store i64 [[TMP2]], ptr [[TMP22]], align 8 | |
| ; CHECK-VF1IC4-NEXT: store i64 [[TMP3]], ptr [[TMP23]], align 8 | |
| ; CHECK-VF1IC4-NEXT: store i64 [[TMP4]], ptr [[TMP24]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP25]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP20:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP45:%.*]] = select i1 [[TMP32]], i32 [[TMP36]], i32 331 | |
| ; CHECK-VF1IC4-NEXT: [[TMP46:%.*]] = select i1 [[TMP33]], i32 [[TMP37]], i32 [[TMP45]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP47:%.*]] = select i1 [[TMP34]], i32 [[TMP38]], i32 [[TMP46]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP48:%.*]] = select i1 [[TMP35]], i32 [[TMP39]], i32 [[TMP47]] | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ [[TMP48]], %[[MIDDLE_BLOCK]] ], [ 331, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1IC4: [[LOOP]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i32 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[GEP_A:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[L:%.*]] = load i32, ptr [[GEP_A]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[L]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TRUNC:%.*]] = trunc i64 [[IV]] to i32 | |
| ; CHECK-VF1IC4-NEXT: [[SEL]] = select i1 [[CMP]], i32 [[TRUNC]], i32 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[GEP_B:%.*]] = getelementptr inbounds i64, ptr [[B]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: store i64 [[IV]], ptr [[GEP_B]], align 8 | |
| ; CHECK-VF1IC4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP21:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SEL_LCSSA:%.*]] = phi i32 [ [[SEL]], %[[LOOP]] ], [ [[TMP48]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i32 [[SEL_LCSSA]] | |
| ; | |
| entry: | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %rdx = phi i32 [ 331, %entry ], [ %sel, %loop ] | |
| %gep.a = getelementptr inbounds i32, ptr %a, i64 %iv | |
| %l = load i32, ptr %gep.a, align 4 | |
| %cmp = icmp sgt i32 %l, 3 | |
| %trunc = trunc i64 %iv to i32 | |
| %sel = select i1 %cmp, i32 %trunc, i32 %rdx | |
| %gep.b = getelementptr inbounds i64, ptr %b, i64 %iv | |
| store i64 %iv, ptr %gep.b, align 8 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %exit.cond = icmp eq i64 %iv.next, %n | |
| br i1 %exit.cond, label %exit, label %loop | |
| exit: | |
| ret i32 %sel | |
| } | |
| ; The truncated IV is always even, so its signed range excludes the sentinel | |
| ; 127, but it wraps, so the last selected value is not the smallest one. | |
| ; FIXME: Currently incorrectly vectorized. | |
| define i8 @select_decreasing_truncated_iv_wraps(ptr %a, i64 %s, i64 %n) { | |
| ; CHECK-VF4IC1-LABEL: define i8 @select_decreasing_truncated_iv_wraps( | |
| ; CHECK-VF4IC1-SAME: ptr [[A:%.*]], i64 [[S:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4IC1-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC1-NEXT: [[START:%.*]] = shl i64 [[S]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF4IC1-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF4IC1-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP1:%.*]] = mul i64 [[N_VEC]], -2 | |
| ; CHECK-VF4IC1-NEXT: [[TMP2:%.*]] = add i64 [[START]], [[TMP1]] | |
| ; CHECK-VF4IC1-NEXT: [[TMP3:%.*]] = trunc i64 [[START]] to i8 | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[TMP3]], i64 0 | |
| ; CHECK-VF4IC1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: [[INDUCTION:%.*]] = add <4 x i8> [[BROADCAST_SPLAT]], <i8 0, i8 -2, i8 -4, i8 -6> | |
| ; CHECK-VF4IC1-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC1: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_PHI:%.*]] = phi <4 x i8> [ splat (i8 127), %[[VECTOR_PH]] ], [ [[TMP6:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-VF4IC1-NEXT: [[TMP6]] = select <4 x i1> [[TMP5]], <4 x i8> [[VEC_IND]], <4 x i8> [[VEC_PHI]] | |
| ; CHECK-VF4IC1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF4IC1-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[VEC_IND]], splat (i8 -8) | |
| ; CHECK-VF4IC1-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[TMP7]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] | |
| ; CHECK-VF4IC1: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC1-NEXT: [[TMP8:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[TMP6]]) | |
| ; CHECK-VF4IC1-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP8]], 127 | |
| ; CHECK-VF4IC1-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i8 [[TMP8]], i8 0 | |
| ; CHECK-VF4IC1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC1: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i64 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: [[BC_MERGE_RDX:%.*]] = phi i8 [ [[TMP10]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC1-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4IC1: [[LOOP]]: | |
| ; CHECK-VF4IC1-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL1]], %[[SCALAR_PH]] ], [ [[WIDE_IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[RDX:%.*]] = phi i8 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC1-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[WIDE_IV]] to i8 | |
| ; CHECK-VF4IC1-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC1-NEXT: [[LD:%.*]] = load i32, ptr [[GEP]], align 4 | |
| ; CHECK-VF4IC1-NEXT: [[CMP:%.*]] = icmp sgt i32 [[LD]], 0 | |
| ; CHECK-VF4IC1-NEXT: [[SEL]] = select i1 [[CMP]], i8 [[TRUNC_IV]], i8 [[RDX]] | |
| ; CHECK-VF4IC1-NEXT: [[WIDE_IV_NEXT]] = add i64 [[WIDE_IV]], -2 | |
| ; CHECK-VF4IC1-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC1-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4IC1-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP23:![0-9]+]] | |
| ; CHECK-VF4IC1: [[EXIT]]: | |
| ; CHECK-VF4IC1-NEXT: [[SEL_LCSSA:%.*]] = phi i8 [ [[SEL]], %[[LOOP]] ], [ [[TMP10]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC1-NEXT: ret i8 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF4IC4-LABEL: define i8 @select_decreasing_truncated_iv_wraps( | |
| ; CHECK-VF4IC4-SAME: ptr [[A:%.*]], i64 [[S:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF4IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF4IC4-NEXT: [[START:%.*]] = shl i64 [[S]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 16 | |
| ; CHECK-VF4IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 15 | |
| ; CHECK-VF4IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP1:%.*]] = mul i64 [[N_VEC]], -2 | |
| ; CHECK-VF4IC4-NEXT: [[TMP2:%.*]] = add i64 [[START]], [[TMP1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP3:%.*]] = trunc i64 [[START]] to i8 | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[TMP3]], i64 0 | |
| ; CHECK-VF4IC4-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[INDUCTION:%.*]] = add <4 x i8> [[BROADCAST_SPLAT]], <i8 0, i8 -2, i8 -4, i8 -6> | |
| ; CHECK-VF4IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF4IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF4IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI:%.*]] = phi <4 x i8> [ splat (i8 127), %[[VECTOR_PH]] ], [ [[TMP12:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i8> [ splat (i8 127), %[[VECTOR_PH]] ], [ [[TMP13:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI2:%.*]] = phi <4 x i8> [ splat (i8 127), %[[VECTOR_PH]] ], [ [[TMP14:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_PHI3:%.*]] = phi <4 x i8> [ splat (i8 127), %[[VECTOR_PH]] ], [ [[TMP15:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND:%.*]] = phi <4 x i8> [ [[INDUCTION]], %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD:%.*]] = add <4 x i8> [[VEC_IND]], splat (i8 -8) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_2:%.*]] = add <4 x i8> [[STEP_ADD]], splat (i8 -8) | |
| ; CHECK-VF4IC4-NEXT: [[STEP_ADD_3:%.*]] = add <4 x i8> [[STEP_ADD_2]], splat (i8 -8) | |
| ; CHECK-VF4IC4-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i64 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[TMP4]], i64 8 | |
| ; CHECK-VF4IC4-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[TMP4]], i64 12 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP4]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[TMP8:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP9:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD4]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP10:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD5]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP11:%.*]] = icmp sgt <4 x i32> [[WIDE_LOAD6]], zeroinitializer | |
| ; CHECK-VF4IC4-NEXT: [[TMP12]] = select <4 x i1> [[TMP8]], <4 x i8> [[VEC_IND]], <4 x i8> [[VEC_PHI]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP13]] = select <4 x i1> [[TMP9]], <4 x i8> [[STEP_ADD]], <4 x i8> [[VEC_PHI1]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP14]] = select <4 x i1> [[TMP10]], <4 x i8> [[STEP_ADD_2]], <4 x i8> [[VEC_PHI2]] | |
| ; CHECK-VF4IC4-NEXT: [[TMP15]] = select <4 x i1> [[TMP11]], <4 x i8> [[STEP_ADD_3]], <4 x i8> [[VEC_PHI3]] | |
| ; CHECK-VF4IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 | |
| ; CHECK-VF4IC4-NEXT: [[VEC_IND_NEXT]] = add <4 x i8> [[STEP_ADD_3]], splat (i8 -8) | |
| ; CHECK-VF4IC4-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[TMP16]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] | |
| ; CHECK-VF4IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[TMP12]], <4 x i8> [[TMP13]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX7:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[RDX_MINMAX]], <4 x i8> [[TMP14]]) | |
| ; CHECK-VF4IC4-NEXT: [[RDX_MINMAX8:%.*]] = call <4 x i8> @llvm.smin.v4i8(<4 x i8> [[RDX_MINMAX7]], <4 x i8> [[TMP15]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP17:%.*]] = call i8 @llvm.vector.reduce.smin.v4i8(<4 x i8> [[RDX_MINMAX8]]) | |
| ; CHECK-VF4IC4-NEXT: [[TMP18:%.*]] = icmp ne i8 [[TMP17]], 127 | |
| ; CHECK-VF4IC4-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i8 [[TMP17]], i8 0 | |
| ; CHECK-VF4IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF4IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_RESUME_VAL9:%.*]] = phi i64 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i8 [ [[TMP19]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF4IC4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF4IC4: [[LOOP]]: | |
| ; CHECK-VF4IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL9]], %[[SCALAR_PH]] ], [ [[WIDE_IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[RDX:%.*]] = phi i8 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF4IC4-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[WIDE_IV]] to i8 | |
| ; CHECK-VF4IC4-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF4IC4-NEXT: [[LD:%.*]] = load i32, ptr [[GEP]], align 4 | |
| ; CHECK-VF4IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[LD]], 0 | |
| ; CHECK-VF4IC4-NEXT: [[SEL]] = select i1 [[CMP]], i8 [[TRUNC_IV]], i8 [[RDX]] | |
| ; CHECK-VF4IC4-NEXT: [[WIDE_IV_NEXT]] = add i64 [[WIDE_IV]], -2 | |
| ; CHECK-VF4IC4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF4IC4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF4IC4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP23:![0-9]+]] | |
| ; CHECK-VF4IC4: [[EXIT]]: | |
| ; CHECK-VF4IC4-NEXT: [[SEL_LCSSA:%.*]] = phi i8 [ [[SEL]], %[[LOOP]] ], [ [[TMP19]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF4IC4-NEXT: ret i8 [[SEL_LCSSA]] | |
| ; | |
| ; CHECK-VF1IC4-LABEL: define i8 @select_decreasing_truncated_iv_wraps( | |
| ; CHECK-VF1IC4-SAME: ptr [[A:%.*]], i64 [[S:%.*]], i64 [[N:%.*]]) { | |
| ; CHECK-VF1IC4-NEXT: [[ENTRY:.*]]: | |
| ; CHECK-VF1IC4-NEXT: [[START:%.*]] = shl i64 [[S]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[N]], 4 | |
| ; CHECK-VF1IC4-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[TMP0:%.*]] = and i64 [[N]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[N_VEC:%.*]] = sub i64 [[N]], [[TMP0]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP1:%.*]] = mul i64 [[N_VEC]], -2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP2:%.*]] = add i64 [[START]], [[TMP1]] | |
| ; CHECK-VF1IC4-NEXT: br label %[[VECTOR_BODY:.*]] | |
| ; CHECK-VF1IC4: [[VECTOR_BODY]]: | |
| ; CHECK-VF1IC4-NEXT: [[INDEX:%.*]] = phi i64 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI:%.*]] = phi i8 [ 127, %[[VECTOR_PH]] ], [ [[TMP24:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI1:%.*]] = phi i8 [ 127, %[[VECTOR_PH]] ], [ [[TMP25:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI2:%.*]] = phi i8 [ 127, %[[VECTOR_PH]] ], [ [[TMP26:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[VEC_PHI3:%.*]] = phi i8 [ 127, %[[VECTOR_PH]] ], [ [[TMP27:%.*]], %[[VECTOR_BODY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 3 | |
| ; CHECK-VF1IC4-NEXT: [[TMP6:%.*]] = mul i64 [[INDEX]], -2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP7:%.*]] = add i64 [[START]], [[TMP6]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i8 | |
| ; CHECK-VF1IC4-NEXT: [[TMP9:%.*]] = add i8 [[TMP8]], -2 | |
| ; CHECK-VF1IC4-NEXT: [[TMP10:%.*]] = add i8 [[TMP8]], -4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP11:%.*]] = add i8 [[TMP8]], -6 | |
| ; CHECK-VF1IC4-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[A]], i64 [[INDEX]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP3]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP4]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[A]], i64 [[TMP5]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP16:%.*]] = load i32, ptr [[TMP12]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP13]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP14]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP19:%.*]] = load i32, ptr [[TMP15]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP20:%.*]] = icmp sgt i32 [[TMP16]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP21:%.*]] = icmp sgt i32 [[TMP17]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP22:%.*]] = icmp sgt i32 [[TMP18]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP23:%.*]] = icmp sgt i32 [[TMP19]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[TMP24]] = select i1 [[TMP20]], i8 [[TMP8]], i8 [[VEC_PHI]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP25]] = select i1 [[TMP21]], i8 [[TMP9]], i8 [[VEC_PHI1]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP26]] = select i1 [[TMP22]], i8 [[TMP10]], i8 [[VEC_PHI2]] | |
| ; CHECK-VF1IC4-NEXT: [[TMP27]] = select i1 [[TMP23]], i8 [[TMP11]], i8 [[VEC_PHI3]] | |
| ; CHECK-VF1IC4-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 | |
| ; CHECK-VF1IC4-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[TMP28]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP22:![0-9]+]] | |
| ; CHECK-VF1IC4: [[MIDDLE_BLOCK]]: | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX:%.*]] = call i8 @llvm.smin.i8(i8 [[TMP24]], i8 [[TMP25]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX4:%.*]] = call i8 @llvm.smin.i8(i8 [[RDX_MINMAX]], i8 [[TMP26]]) | |
| ; CHECK-VF1IC4-NEXT: [[RDX_MINMAX5:%.*]] = call i8 @llvm.smin.i8(i8 [[RDX_MINMAX4]], i8 [[TMP27]]) | |
| ; CHECK-VF1IC4-NEXT: [[TMP29:%.*]] = icmp ne i8 [[RDX_MINMAX5]], 127 | |
| ; CHECK-VF1IC4-NEXT: [[TMP30:%.*]] = select i1 [[TMP29]], i8 [[RDX_MINMAX5]], i8 0 | |
| ; CHECK-VF1IC4-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[N]], [[N_VEC]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[CMP_N]], label %[[EXIT:.*]], label %[[SCALAR_PH]] | |
| ; CHECK-VF1IC4: [[SCALAR_PH]]: | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_RESUME_VAL6:%.*]] = phi i64 [ [[TMP2]], %[[MIDDLE_BLOCK]] ], [ [[START]], %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: [[BC_MERGE_RDX:%.*]] = phi i8 [ [[TMP30]], %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ] | |
| ; CHECK-VF1IC4-NEXT: br label %[[LOOP:.*]] | |
| ; CHECK-VF1IC4: [[LOOP]]: | |
| ; CHECK-VF1IC4-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[WIDE_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL6]], %[[SCALAR_PH]] ], [ [[WIDE_IV_NEXT:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[RDX:%.*]] = phi i8 [ [[BC_MERGE_RDX]], %[[SCALAR_PH]] ], [ [[SEL:%.*]], %[[LOOP]] ] | |
| ; CHECK-VF1IC4-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[WIDE_IV]] to i8 | |
| ; CHECK-VF1IC4-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[A]], i64 [[IV]] | |
| ; CHECK-VF1IC4-NEXT: [[LD:%.*]] = load i32, ptr [[GEP]], align 4 | |
| ; CHECK-VF1IC4-NEXT: [[CMP:%.*]] = icmp sgt i32 [[LD]], 0 | |
| ; CHECK-VF1IC4-NEXT: [[SEL]] = select i1 [[CMP]], i8 [[TRUNC_IV]], i8 [[RDX]] | |
| ; CHECK-VF1IC4-NEXT: [[WIDE_IV_NEXT]] = add i64 [[WIDE_IV]], -2 | |
| ; CHECK-VF1IC4-NEXT: [[IV_NEXT]] = add nuw nsw i64 [[IV]], 1 | |
| ; CHECK-VF1IC4-NEXT: [[EXIT_COND:%.*]] = icmp eq i64 [[IV_NEXT]], [[N]] | |
| ; CHECK-VF1IC4-NEXT: br i1 [[EXIT_COND]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP23:![0-9]+]] | |
| ; CHECK-VF1IC4: [[EXIT]]: | |
| ; CHECK-VF1IC4-NEXT: [[SEL_LCSSA:%.*]] = phi i8 [ [[SEL]], %[[LOOP]] ], [ [[TMP30]], %[[MIDDLE_BLOCK]] ] | |
| ; CHECK-VF1IC4-NEXT: ret i8 [[SEL_LCSSA]] | |
| ; | |
| entry: | |
| %start = shl i64 %s, 1 | |
| br label %loop | |
| loop: | |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] | |
| %wide.iv = phi i64 [ %start, %entry ], [ %wide.iv.next, %loop ] | |
| %rdx = phi i8 [ 0, %entry ], [ %sel, %loop ] | |
| %trunc.iv = trunc i64 %wide.iv to i8 | |
| %gep = getelementptr i32, ptr %a, i64 %iv | |
| %ld = load i32, ptr %gep, align 4 | |
| %cmp = icmp sgt i32 %ld, 0 | |
| %sel = select i1 %cmp, i8 %trunc.iv, i8 %rdx | |
| %wide.iv.next = add i64 %wide.iv, -2 | |
| %iv.next = add nuw nsw i64 %iv, 1 | |
| %exit.cond = icmp eq i64 %iv.next, %n | |
| br i1 %exit.cond, label %exit, label %loop | |
| exit: | |
| ret i8 %sel | |
| } |