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llvm/llvm-project/792bf8ef030d7c2aa12abbab7662ffbcbe2d8b21/./llvm/test/Transforms/LoopVectorize/WebAssembly/blake2.ll
blob: 6f2d96a1291f6dd6e4172669791def365a62f264 [file]
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt -mtriple=wasm32 -mattr=+simd128 -passes=loop-vectorize -S %s -o - | FileCheck %s
define dso_local void @fill_block_with_xor(ptr %arg) {
; CHECK-LABEL: define dso_local void @fill_block_with_xor(
; CHECK-SAME: ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT: [[NEWFUNCROOT:.*:]]
; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
; CHECK: [[VECTOR_BODY]]:
; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
; CHECK-NEXT: [[TMP0:%.*]] = shl nuw nsw i32 [[INDEX]], 4
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[ARG]], i32 [[TMP0]]
; CHECK-NEXT: [[WIDE_VEC:%.*]] = load <4 x i64>, ptr [[TMP1]], align 8
; CHECK-NEXT: [[STRIDED_VEC:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC1:%.*]] = shufflevector <4 x i64> [[WIDE_VEC]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[TMP1]], i32 256
; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load <4 x i64>, ptr [[TMP2]], align 8
; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC4:%.*]] = shufflevector <4 x i64> [[WIDE_VEC2]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP3:%.*]] = and <2 x i64> [[STRIDED_VEC3]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP4:%.*]] = add <2 x i64> [[STRIDED_VEC3]], [[STRIDED_VEC]]
; CHECK-NEXT: [[TMP5:%.*]] = shl <2 x i64> [[STRIDED_VEC]], splat (i64 1)
; CHECK-NEXT: [[TMP6:%.*]] = and <2 x i64> [[TMP5]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP7:%.*]] = mul <2 x i64> [[TMP6]], [[TMP3]]
; CHECK-NEXT: [[TMP8:%.*]] = add <2 x i64> [[TMP4]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP1]], i32 768
; CHECK-NEXT: [[WIDE_VEC5:%.*]] = load <4 x i64>, ptr [[TMP9]], align 8
; CHECK-NEXT: [[STRIDED_VEC6:%.*]] = shufflevector <4 x i64> [[WIDE_VEC5]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC7:%.*]] = shufflevector <4 x i64> [[WIDE_VEC5]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP10:%.*]] = xor <2 x i64> [[TMP8]], [[STRIDED_VEC6]]
; CHECK-NEXT: [[TMP11:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP10]], <2 x i64> [[TMP10]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP1]], i32 512
; CHECK-NEXT: [[WIDE_VEC8:%.*]] = load <4 x i64>, ptr [[TMP12]], align 8
; CHECK-NEXT: [[STRIDED_VEC9:%.*]] = shufflevector <4 x i64> [[WIDE_VEC8]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC10:%.*]] = shufflevector <4 x i64> [[WIDE_VEC8]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP13:%.*]] = and <2 x i64> [[TMP11]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP14:%.*]] = add <2 x i64> [[TMP11]], [[STRIDED_VEC9]]
; CHECK-NEXT: [[TMP15:%.*]] = shl <2 x i64> [[STRIDED_VEC9]], splat (i64 1)
; CHECK-NEXT: [[TMP16:%.*]] = and <2 x i64> [[TMP15]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP17:%.*]] = mul <2 x i64> [[TMP16]], [[TMP13]]
; CHECK-NEXT: [[TMP18:%.*]] = add <2 x i64> [[TMP14]], [[TMP17]]
; CHECK-NEXT: [[TMP19:%.*]] = xor <2 x i64> [[TMP18]], [[STRIDED_VEC3]]
; CHECK-NEXT: [[TMP20:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP19]], <2 x i64> [[TMP19]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP21:%.*]] = and <2 x i64> [[TMP20]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP22:%.*]] = add <2 x i64> [[TMP20]], [[TMP8]]
; CHECK-NEXT: [[TMP23:%.*]] = shl <2 x i64> [[TMP8]], splat (i64 1)
; CHECK-NEXT: [[TMP24:%.*]] = and <2 x i64> [[TMP23]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP25:%.*]] = mul <2 x i64> [[TMP21]], [[TMP24]]
; CHECK-NEXT: [[TMP26:%.*]] = add <2 x i64> [[TMP22]], [[TMP25]]
; CHECK-NEXT: [[TMP27:%.*]] = xor <2 x i64> [[TMP26]], [[TMP11]]
; CHECK-NEXT: [[TMP28:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP27]], <2 x i64> [[TMP27]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP29:%.*]] = and <2 x i64> [[TMP28]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP30:%.*]] = add <2 x i64> [[TMP28]], [[TMP18]]
; CHECK-NEXT: [[TMP31:%.*]] = shl <2 x i64> [[TMP18]], splat (i64 1)
; CHECK-NEXT: [[TMP32:%.*]] = and <2 x i64> [[TMP31]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP33:%.*]] = mul <2 x i64> [[TMP29]], [[TMP32]]
; CHECK-NEXT: [[TMP34:%.*]] = add <2 x i64> [[TMP30]], [[TMP33]]
; CHECK-NEXT: [[TMP35:%.*]] = xor <2 x i64> [[TMP34]], [[TMP20]]
; CHECK-NEXT: [[TMP36:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP35]], <2 x i64> [[TMP35]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP37:%.*]] = and <2 x i64> [[STRIDED_VEC4]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP38:%.*]] = add <2 x i64> [[STRIDED_VEC4]], [[STRIDED_VEC1]]
; CHECK-NEXT: [[TMP39:%.*]] = shl <2 x i64> [[STRIDED_VEC1]], splat (i64 1)
; CHECK-NEXT: [[TMP40:%.*]] = and <2 x i64> [[TMP39]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP41:%.*]] = mul <2 x i64> [[TMP40]], [[TMP37]]
; CHECK-NEXT: [[TMP42:%.*]] = add <2 x i64> [[TMP38]], [[TMP41]]
; CHECK-NEXT: [[TMP43:%.*]] = xor <2 x i64> [[TMP42]], [[STRIDED_VEC7]]
; CHECK-NEXT: [[TMP44:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP43]], <2 x i64> [[TMP43]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP45:%.*]] = and <2 x i64> [[TMP44]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP46:%.*]] = add <2 x i64> [[TMP44]], [[STRIDED_VEC10]]
; CHECK-NEXT: [[TMP47:%.*]] = shl <2 x i64> [[STRIDED_VEC10]], splat (i64 1)
; CHECK-NEXT: [[TMP48:%.*]] = and <2 x i64> [[TMP47]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP49:%.*]] = mul <2 x i64> [[TMP48]], [[TMP45]]
; CHECK-NEXT: [[TMP50:%.*]] = add <2 x i64> [[TMP46]], [[TMP49]]
; CHECK-NEXT: [[TMP51:%.*]] = xor <2 x i64> [[TMP50]], [[STRIDED_VEC4]]
; CHECK-NEXT: [[TMP52:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP51]], <2 x i64> [[TMP51]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP53:%.*]] = and <2 x i64> [[TMP52]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP54:%.*]] = add <2 x i64> [[TMP52]], [[TMP42]]
; CHECK-NEXT: [[TMP55:%.*]] = shl <2 x i64> [[TMP42]], splat (i64 1)
; CHECK-NEXT: [[TMP56:%.*]] = and <2 x i64> [[TMP55]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP57:%.*]] = mul <2 x i64> [[TMP53]], [[TMP56]]
; CHECK-NEXT: [[TMP58:%.*]] = add <2 x i64> [[TMP54]], [[TMP57]]
; CHECK-NEXT: [[TMP59:%.*]] = xor <2 x i64> [[TMP58]], [[TMP44]]
; CHECK-NEXT: [[TMP60:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP59]], <2 x i64> [[TMP59]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP61:%.*]] = and <2 x i64> [[TMP60]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP62:%.*]] = add <2 x i64> [[TMP60]], [[TMP50]]
; CHECK-NEXT: [[TMP63:%.*]] = shl <2 x i64> [[TMP50]], splat (i64 1)
; CHECK-NEXT: [[TMP64:%.*]] = and <2 x i64> [[TMP63]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP65:%.*]] = mul <2 x i64> [[TMP61]], [[TMP64]]
; CHECK-NEXT: [[TMP66:%.*]] = add <2 x i64> [[TMP62]], [[TMP65]]
; CHECK-NEXT: [[TMP67:%.*]] = xor <2 x i64> [[TMP66]], [[TMP52]]
; CHECK-NEXT: [[TMP68:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP67]], <2 x i64> [[TMP67]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP69:%.*]] = getelementptr i8, ptr [[TMP1]], i32 128
; CHECK-NEXT: [[WIDE_VEC11:%.*]] = load <4 x i64>, ptr [[TMP69]], align 8
; CHECK-NEXT: [[STRIDED_VEC12:%.*]] = shufflevector <4 x i64> [[WIDE_VEC11]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC13:%.*]] = shufflevector <4 x i64> [[WIDE_VEC11]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP70:%.*]] = getelementptr i8, ptr [[TMP1]], i32 384
; CHECK-NEXT: [[WIDE_VEC14:%.*]] = load <4 x i64>, ptr [[TMP70]], align 8
; CHECK-NEXT: [[STRIDED_VEC15:%.*]] = shufflevector <4 x i64> [[WIDE_VEC14]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC16:%.*]] = shufflevector <4 x i64> [[WIDE_VEC14]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP71:%.*]] = and <2 x i64> [[STRIDED_VEC15]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP72:%.*]] = add <2 x i64> [[STRIDED_VEC15]], [[STRIDED_VEC12]]
; CHECK-NEXT: [[TMP73:%.*]] = shl <2 x i64> [[STRIDED_VEC12]], splat (i64 1)
; CHECK-NEXT: [[TMP74:%.*]] = and <2 x i64> [[TMP73]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP75:%.*]] = mul <2 x i64> [[TMP74]], [[TMP71]]
; CHECK-NEXT: [[TMP76:%.*]] = add <2 x i64> [[TMP72]], [[TMP75]]
; CHECK-NEXT: [[TMP77:%.*]] = getelementptr i8, ptr [[TMP1]], i32 896
; CHECK-NEXT: [[WIDE_VEC17:%.*]] = load <4 x i64>, ptr [[TMP77]], align 8
; CHECK-NEXT: [[STRIDED_VEC18:%.*]] = shufflevector <4 x i64> [[WIDE_VEC17]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC19:%.*]] = shufflevector <4 x i64> [[WIDE_VEC17]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP78:%.*]] = xor <2 x i64> [[TMP76]], [[STRIDED_VEC18]]
; CHECK-NEXT: [[TMP79:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP78]], <2 x i64> [[TMP78]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP80:%.*]] = getelementptr i8, ptr [[TMP1]], i32 640
; CHECK-NEXT: [[WIDE_VEC20:%.*]] = load <4 x i64>, ptr [[TMP80]], align 8
; CHECK-NEXT: [[STRIDED_VEC21:%.*]] = shufflevector <4 x i64> [[WIDE_VEC20]], <4 x i64> poison, <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: [[STRIDED_VEC22:%.*]] = shufflevector <4 x i64> [[WIDE_VEC20]], <4 x i64> poison, <2 x i32> <i32 1, i32 3>
; CHECK-NEXT: [[TMP81:%.*]] = and <2 x i64> [[TMP79]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP82:%.*]] = add <2 x i64> [[TMP79]], [[STRIDED_VEC21]]
; CHECK-NEXT: [[TMP83:%.*]] = shl <2 x i64> [[STRIDED_VEC21]], splat (i64 1)
; CHECK-NEXT: [[TMP84:%.*]] = and <2 x i64> [[TMP83]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP85:%.*]] = mul <2 x i64> [[TMP84]], [[TMP81]]
; CHECK-NEXT: [[TMP86:%.*]] = add <2 x i64> [[TMP82]], [[TMP85]]
; CHECK-NEXT: [[TMP87:%.*]] = xor <2 x i64> [[TMP86]], [[STRIDED_VEC15]]
; CHECK-NEXT: [[TMP88:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP87]], <2 x i64> [[TMP87]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP89:%.*]] = and <2 x i64> [[TMP88]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP90:%.*]] = add <2 x i64> [[TMP88]], [[TMP76]]
; CHECK-NEXT: [[TMP91:%.*]] = shl <2 x i64> [[TMP76]], splat (i64 1)
; CHECK-NEXT: [[TMP92:%.*]] = and <2 x i64> [[TMP91]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP93:%.*]] = mul <2 x i64> [[TMP89]], [[TMP92]]
; CHECK-NEXT: [[TMP94:%.*]] = add <2 x i64> [[TMP90]], [[TMP93]]
; CHECK-NEXT: [[TMP95:%.*]] = xor <2 x i64> [[TMP94]], [[TMP79]]
; CHECK-NEXT: [[TMP96:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP95]], <2 x i64> [[TMP95]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP97:%.*]] = and <2 x i64> [[TMP96]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP98:%.*]] = add <2 x i64> [[TMP96]], [[TMP86]]
; CHECK-NEXT: [[TMP99:%.*]] = shl <2 x i64> [[TMP86]], splat (i64 1)
; CHECK-NEXT: [[TMP100:%.*]] = and <2 x i64> [[TMP99]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP101:%.*]] = mul <2 x i64> [[TMP97]], [[TMP100]]
; CHECK-NEXT: [[TMP102:%.*]] = add <2 x i64> [[TMP98]], [[TMP101]]
; CHECK-NEXT: [[TMP103:%.*]] = xor <2 x i64> [[TMP102]], [[TMP88]]
; CHECK-NEXT: [[TMP104:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP103]], <2 x i64> [[TMP103]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP105:%.*]] = and <2 x i64> [[STRIDED_VEC16]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP106:%.*]] = add <2 x i64> [[STRIDED_VEC16]], [[STRIDED_VEC13]]
; CHECK-NEXT: [[TMP107:%.*]] = shl <2 x i64> [[STRIDED_VEC13]], splat (i64 1)
; CHECK-NEXT: [[TMP108:%.*]] = and <2 x i64> [[TMP107]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP109:%.*]] = mul <2 x i64> [[TMP108]], [[TMP105]]
; CHECK-NEXT: [[TMP110:%.*]] = add <2 x i64> [[TMP106]], [[TMP109]]
; CHECK-NEXT: [[TMP111:%.*]] = xor <2 x i64> [[TMP110]], [[STRIDED_VEC19]]
; CHECK-NEXT: [[TMP112:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP111]], <2 x i64> [[TMP111]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP113:%.*]] = and <2 x i64> [[TMP112]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP114:%.*]] = add <2 x i64> [[TMP112]], [[STRIDED_VEC22]]
; CHECK-NEXT: [[TMP115:%.*]] = shl <2 x i64> [[STRIDED_VEC22]], splat (i64 1)
; CHECK-NEXT: [[TMP116:%.*]] = and <2 x i64> [[TMP115]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP117:%.*]] = mul <2 x i64> [[TMP116]], [[TMP113]]
; CHECK-NEXT: [[TMP118:%.*]] = add <2 x i64> [[TMP114]], [[TMP117]]
; CHECK-NEXT: [[TMP119:%.*]] = xor <2 x i64> [[TMP118]], [[STRIDED_VEC16]]
; CHECK-NEXT: [[TMP120:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP119]], <2 x i64> [[TMP119]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP121:%.*]] = and <2 x i64> [[TMP120]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP122:%.*]] = add <2 x i64> [[TMP120]], [[TMP110]]
; CHECK-NEXT: [[TMP123:%.*]] = shl <2 x i64> [[TMP110]], splat (i64 1)
; CHECK-NEXT: [[TMP124:%.*]] = and <2 x i64> [[TMP123]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP125:%.*]] = mul <2 x i64> [[TMP121]], [[TMP124]]
; CHECK-NEXT: [[TMP126:%.*]] = add <2 x i64> [[TMP122]], [[TMP125]]
; CHECK-NEXT: [[TMP127:%.*]] = xor <2 x i64> [[TMP126]], [[TMP112]]
; CHECK-NEXT: [[TMP128:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP127]], <2 x i64> [[TMP127]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP129:%.*]] = and <2 x i64> [[TMP128]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP130:%.*]] = add <2 x i64> [[TMP128]], [[TMP118]]
; CHECK-NEXT: [[TMP131:%.*]] = shl <2 x i64> [[TMP118]], splat (i64 1)
; CHECK-NEXT: [[TMP132:%.*]] = and <2 x i64> [[TMP131]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP133:%.*]] = mul <2 x i64> [[TMP129]], [[TMP132]]
; CHECK-NEXT: [[TMP134:%.*]] = add <2 x i64> [[TMP130]], [[TMP133]]
; CHECK-NEXT: [[TMP135:%.*]] = xor <2 x i64> [[TMP134]], [[TMP120]]
; CHECK-NEXT: [[TMP136:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP135]], <2 x i64> [[TMP135]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP137:%.*]] = and <2 x i64> [[TMP68]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP138:%.*]] = add <2 x i64> [[TMP68]], [[TMP26]]
; CHECK-NEXT: [[TMP139:%.*]] = shl <2 x i64> [[TMP26]], splat (i64 1)
; CHECK-NEXT: [[TMP140:%.*]] = and <2 x i64> [[TMP139]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP141:%.*]] = mul <2 x i64> [[TMP137]], [[TMP140]]
; CHECK-NEXT: [[TMP142:%.*]] = add <2 x i64> [[TMP138]], [[TMP141]]
; CHECK-NEXT: [[TMP143:%.*]] = xor <2 x i64> [[TMP128]], [[TMP142]]
; CHECK-NEXT: [[TMP144:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP143]], <2 x i64> [[TMP143]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP145:%.*]] = and <2 x i64> [[TMP144]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP146:%.*]] = add <2 x i64> [[TMP144]], [[TMP102]]
; CHECK-NEXT: [[TMP147:%.*]] = shl <2 x i64> [[TMP102]], splat (i64 1)
; CHECK-NEXT: [[TMP148:%.*]] = and <2 x i64> [[TMP147]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP149:%.*]] = mul <2 x i64> [[TMP145]], [[TMP148]]
; CHECK-NEXT: [[TMP150:%.*]] = add <2 x i64> [[TMP146]], [[TMP149]]
; CHECK-NEXT: [[TMP151:%.*]] = xor <2 x i64> [[TMP150]], [[TMP68]]
; CHECK-NEXT: [[TMP152:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP151]], <2 x i64> [[TMP151]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP153:%.*]] = and <2 x i64> [[TMP152]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP154:%.*]] = add <2 x i64> [[TMP152]], [[TMP142]]
; CHECK-NEXT: [[TMP155:%.*]] = shl <2 x i64> [[TMP142]], splat (i64 1)
; CHECK-NEXT: [[TMP156:%.*]] = and <2 x i64> [[TMP155]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP157:%.*]] = mul <2 x i64> [[TMP153]], [[TMP156]]
; CHECK-NEXT: [[TMP158:%.*]] = add <2 x i64> [[TMP154]], [[TMP157]]
; CHECK-NEXT: [[TMP159:%.*]] = xor <2 x i64> [[TMP158]], [[TMP144]]
; CHECK-NEXT: [[TMP160:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP159]], <2 x i64> [[TMP159]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP161:%.*]] = and <2 x i64> [[TMP160]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP162:%.*]] = add <2 x i64> [[TMP160]], [[TMP150]]
; CHECK-NEXT: [[TMP163:%.*]] = shl <2 x i64> [[TMP150]], splat (i64 1)
; CHECK-NEXT: [[TMP164:%.*]] = and <2 x i64> [[TMP163]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP165:%.*]] = mul <2 x i64> [[TMP161]], [[TMP164]]
; CHECK-NEXT: [[TMP166:%.*]] = add <2 x i64> [[TMP162]], [[TMP165]]
; CHECK-NEXT: [[TMP167:%.*]] = xor <2 x i64> [[TMP166]], [[TMP152]]
; CHECK-NEXT: [[TMP168:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP167]], <2 x i64> [[TMP167]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP169:%.*]] = and <2 x i64> [[TMP104]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP170:%.*]] = add <2 x i64> [[TMP104]], [[TMP58]]
; CHECK-NEXT: [[TMP171:%.*]] = shl <2 x i64> [[TMP58]], splat (i64 1)
; CHECK-NEXT: [[TMP172:%.*]] = and <2 x i64> [[TMP171]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP173:%.*]] = mul <2 x i64> [[TMP169]], [[TMP172]]
; CHECK-NEXT: [[TMP174:%.*]] = add <2 x i64> [[TMP170]], [[TMP173]]
; CHECK-NEXT: [[TMP175:%.*]] = xor <2 x i64> [[TMP174]], [[TMP28]]
; CHECK-NEXT: [[TMP176:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP175]], <2 x i64> [[TMP175]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP177:%.*]] = and <2 x i64> [[TMP176]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP178:%.*]] = add <2 x i64> [[TMP134]], [[TMP176]]
; CHECK-NEXT: [[TMP179:%.*]] = shl <2 x i64> [[TMP134]], splat (i64 1)
; CHECK-NEXT: [[TMP180:%.*]] = and <2 x i64> [[TMP179]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP181:%.*]] = mul <2 x i64> [[TMP180]], [[TMP177]]
; CHECK-NEXT: [[TMP182:%.*]] = add <2 x i64> [[TMP178]], [[TMP181]]
; CHECK-NEXT: [[TMP183:%.*]] = xor <2 x i64> [[TMP182]], [[TMP104]]
; CHECK-NEXT: [[TMP184:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP183]], <2 x i64> [[TMP183]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP185:%.*]] = and <2 x i64> [[TMP184]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP186:%.*]] = add <2 x i64> [[TMP184]], [[TMP174]]
; CHECK-NEXT: [[TMP187:%.*]] = shl <2 x i64> [[TMP174]], splat (i64 1)
; CHECK-NEXT: [[TMP188:%.*]] = and <2 x i64> [[TMP187]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP189:%.*]] = mul <2 x i64> [[TMP185]], [[TMP188]]
; CHECK-NEXT: [[TMP190:%.*]] = add <2 x i64> [[TMP186]], [[TMP189]]
; CHECK-NEXT: [[TMP191:%.*]] = shufflevector <2 x i64> [[TMP158]], <2 x i64> [[TMP190]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = shufflevector <4 x i64> [[TMP191]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC]], ptr [[TMP1]], align 8
; CHECK-NEXT: [[TMP192:%.*]] = xor <2 x i64> [[TMP190]], [[TMP176]]
; CHECK-NEXT: [[TMP193:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP192]], <2 x i64> [[TMP192]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP194:%.*]] = and <2 x i64> [[TMP193]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP195:%.*]] = add <2 x i64> [[TMP193]], [[TMP182]]
; CHECK-NEXT: [[TMP196:%.*]] = shl <2 x i64> [[TMP182]], splat (i64 1)
; CHECK-NEXT: [[TMP197:%.*]] = and <2 x i64> [[TMP196]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP198:%.*]] = mul <2 x i64> [[TMP194]], [[TMP197]]
; CHECK-NEXT: [[TMP199:%.*]] = add <2 x i64> [[TMP195]], [[TMP198]]
; CHECK-NEXT: [[TMP200:%.*]] = shufflevector <2 x i64> [[TMP166]], <2 x i64> [[TMP199]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC23:%.*]] = shufflevector <4 x i64> [[TMP200]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC23]], ptr [[TMP80]], align 8
; CHECK-NEXT: [[TMP201:%.*]] = xor <2 x i64> [[TMP199]], [[TMP184]]
; CHECK-NEXT: [[TMP202:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP201]], <2 x i64> [[TMP201]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP203:%.*]] = and <2 x i64> [[TMP136]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP204:%.*]] = add <2 x i64> [[TMP136]], [[TMP94]]
; CHECK-NEXT: [[TMP205:%.*]] = shl <2 x i64> [[TMP94]], splat (i64 1)
; CHECK-NEXT: [[TMP206:%.*]] = and <2 x i64> [[TMP205]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP207:%.*]] = mul <2 x i64> [[TMP203]], [[TMP206]]
; CHECK-NEXT: [[TMP208:%.*]] = add <2 x i64> [[TMP204]], [[TMP207]]
; CHECK-NEXT: [[TMP209:%.*]] = xor <2 x i64> [[TMP208]], [[TMP60]]
; CHECK-NEXT: [[TMP210:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP209]], <2 x i64> [[TMP209]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP211:%.*]] = and <2 x i64> [[TMP210]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP212:%.*]] = add <2 x i64> [[TMP210]], [[TMP34]]
; CHECK-NEXT: [[TMP213:%.*]] = shl <2 x i64> [[TMP34]], splat (i64 1)
; CHECK-NEXT: [[TMP214:%.*]] = and <2 x i64> [[TMP213]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP215:%.*]] = mul <2 x i64> [[TMP211]], [[TMP214]]
; CHECK-NEXT: [[TMP216:%.*]] = add <2 x i64> [[TMP212]], [[TMP215]]
; CHECK-NEXT: [[TMP217:%.*]] = xor <2 x i64> [[TMP216]], [[TMP136]]
; CHECK-NEXT: [[TMP218:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP217]], <2 x i64> [[TMP217]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP219:%.*]] = and <2 x i64> [[TMP218]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP220:%.*]] = add <2 x i64> [[TMP218]], [[TMP208]]
; CHECK-NEXT: [[TMP221:%.*]] = shl <2 x i64> [[TMP208]], splat (i64 1)
; CHECK-NEXT: [[TMP222:%.*]] = and <2 x i64> [[TMP221]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP223:%.*]] = mul <2 x i64> [[TMP219]], [[TMP222]]
; CHECK-NEXT: [[TMP224:%.*]] = add <2 x i64> [[TMP220]], [[TMP223]]
; CHECK-NEXT: [[TMP225:%.*]] = xor <2 x i64> [[TMP224]], [[TMP210]]
; CHECK-NEXT: [[TMP226:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP225]], <2 x i64> [[TMP225]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP227:%.*]] = shufflevector <2 x i64> [[TMP193]], <2 x i64> [[TMP226]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC24:%.*]] = shufflevector <4 x i64> [[TMP227]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC24]], ptr [[TMP9]], align 8
; CHECK-NEXT: [[TMP228:%.*]] = and <2 x i64> [[TMP226]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP229:%.*]] = add <2 x i64> [[TMP226]], [[TMP216]]
; CHECK-NEXT: [[TMP230:%.*]] = shl <2 x i64> [[TMP216]], splat (i64 1)
; CHECK-NEXT: [[TMP231:%.*]] = and <2 x i64> [[TMP230]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP232:%.*]] = mul <2 x i64> [[TMP228]], [[TMP231]]
; CHECK-NEXT: [[TMP233:%.*]] = add <2 x i64> [[TMP229]], [[TMP232]]
; CHECK-NEXT: [[TMP234:%.*]] = xor <2 x i64> [[TMP233]], [[TMP218]]
; CHECK-NEXT: [[TMP235:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP234]], <2 x i64> [[TMP234]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP236:%.*]] = shufflevector <2 x i64> [[TMP202]], <2 x i64> [[TMP235]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC25:%.*]] = shufflevector <4 x i64> [[TMP236]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC25]], ptr [[TMP70]], align 8
; CHECK-NEXT: [[TMP237:%.*]] = and <2 x i64> [[TMP36]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP238:%.*]] = add <2 x i64> [[TMP126]], [[TMP36]]
; CHECK-NEXT: [[TMP239:%.*]] = shl <2 x i64> [[TMP126]], splat (i64 1)
; CHECK-NEXT: [[TMP240:%.*]] = and <2 x i64> [[TMP239]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP241:%.*]] = mul <2 x i64> [[TMP240]], [[TMP237]]
; CHECK-NEXT: [[TMP242:%.*]] = add <2 x i64> [[TMP238]], [[TMP241]]
; CHECK-NEXT: [[TMP243:%.*]] = xor <2 x i64> [[TMP242]], [[TMP96]]
; CHECK-NEXT: [[TMP244:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP243]], <2 x i64> [[TMP243]], <2 x i64> splat (i64 32))
; CHECK-NEXT: [[TMP245:%.*]] = and <2 x i64> [[TMP244]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP246:%.*]] = add <2 x i64> [[TMP244]], [[TMP66]]
; CHECK-NEXT: [[TMP247:%.*]] = shl <2 x i64> [[TMP66]], splat (i64 1)
; CHECK-NEXT: [[TMP248:%.*]] = and <2 x i64> [[TMP247]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP249:%.*]] = mul <2 x i64> [[TMP245]], [[TMP248]]
; CHECK-NEXT: [[TMP250:%.*]] = add <2 x i64> [[TMP246]], [[TMP249]]
; CHECK-NEXT: [[TMP251:%.*]] = xor <2 x i64> [[TMP250]], [[TMP36]]
; CHECK-NEXT: [[TMP252:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP251]], <2 x i64> [[TMP251]], <2 x i64> splat (i64 40))
; CHECK-NEXT: [[TMP253:%.*]] = and <2 x i64> [[TMP252]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP254:%.*]] = add <2 x i64> [[TMP252]], [[TMP242]]
; CHECK-NEXT: [[TMP255:%.*]] = shl <2 x i64> [[TMP242]], splat (i64 1)
; CHECK-NEXT: [[TMP256:%.*]] = and <2 x i64> [[TMP255]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP257:%.*]] = mul <2 x i64> [[TMP253]], [[TMP256]]
; CHECK-NEXT: [[TMP258:%.*]] = add <2 x i64> [[TMP254]], [[TMP257]]
; CHECK-NEXT: [[TMP259:%.*]] = shufflevector <2 x i64> [[TMP224]], <2 x i64> [[TMP258]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC26:%.*]] = shufflevector <4 x i64> [[TMP259]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC26]], ptr [[TMP69]], align 8
; CHECK-NEXT: [[TMP260:%.*]] = xor <2 x i64> [[TMP258]], [[TMP244]]
; CHECK-NEXT: [[TMP261:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP260]], <2 x i64> [[TMP260]], <2 x i64> splat (i64 48))
; CHECK-NEXT: [[TMP262:%.*]] = shufflevector <2 x i64> [[TMP261]], <2 x i64> [[TMP160]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC27:%.*]] = shufflevector <4 x i64> [[TMP262]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC27]], ptr [[TMP77]], align 8
; CHECK-NEXT: [[TMP263:%.*]] = and <2 x i64> [[TMP261]], splat (i64 4294967295)
; CHECK-NEXT: [[TMP264:%.*]] = add <2 x i64> [[TMP261]], [[TMP250]]
; CHECK-NEXT: [[TMP265:%.*]] = shl <2 x i64> [[TMP250]], splat (i64 1)
; CHECK-NEXT: [[TMP266:%.*]] = and <2 x i64> [[TMP265]], splat (i64 8589934590)
; CHECK-NEXT: [[TMP267:%.*]] = mul <2 x i64> [[TMP263]], [[TMP266]]
; CHECK-NEXT: [[TMP268:%.*]] = add <2 x i64> [[TMP264]], [[TMP267]]
; CHECK-NEXT: [[TMP269:%.*]] = shufflevector <2 x i64> [[TMP233]], <2 x i64> [[TMP268]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC28:%.*]] = shufflevector <4 x i64> [[TMP269]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC28]], ptr [[TMP12]], align 8
; CHECK-NEXT: [[TMP270:%.*]] = xor <2 x i64> [[TMP268]], [[TMP252]]
; CHECK-NEXT: [[TMP271:%.*]] = call <2 x i64> @llvm.fshl.v2i64(<2 x i64> [[TMP270]], <2 x i64> [[TMP270]], <2 x i64> splat (i64 1))
; CHECK-NEXT: [[TMP272:%.*]] = shufflevector <2 x i64> [[TMP271]], <2 x i64> [[TMP168]], <4 x i32> <i32 0, i32 1, i32 2, i32 3>
; CHECK-NEXT: [[INTERLEAVED_VEC29:%.*]] = shufflevector <4 x i64> [[TMP272]], <4 x i64> poison, <4 x i32> <i32 0, i32 2, i32 1, i32 3>
; CHECK-NEXT: store <4 x i64> [[INTERLEAVED_VEC29]], ptr [[TMP2]], align 8
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 2
; CHECK-NEXT: [[TMP273:%.*]] = icmp eq i32 [[INDEX_NEXT]], 8
; CHECK-NEXT: br i1 [[TMP273]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: br label %[[DOTEXITSTUB:.*]]
; CHECK: [[DOTEXITSTUB]]:
; CHECK-NEXT: ret void
;
newFuncRoot:
br label %bb
bb: ; preds = %bb, %newFuncRoot
%i = phi i32 [ %i290, %bb ], [ 0, %newFuncRoot ]
%i1 = shl nuw nsw i32 %i, 4
%i2 = getelementptr i8, ptr %arg, i32 %i1
%i3 = load i64, ptr %i2, align 8
%i4 = getelementptr i8, ptr %i2, i32 256
%i5 = load i64, ptr %i4, align 8
%i6 = and i64 %i5, 4294967295
%i7 = add i64 %i5, %i3
%i8 = shl i64 %i3, 1
%i9 = and i64 %i8, 8589934590
%i10 = mul i64 %i9, %i6
%i11 = add i64 %i7, %i10
%i12 = getelementptr i8, ptr %i2, i32 768
%i13 = load i64, ptr %i12, align 8
%i14 = xor i64 %i11, %i13
%i15 = tail call i64 @llvm.fshl.i64(i64 %i14, i64 %i14, i64 32)
%i16 = getelementptr i8, ptr %i2, i32 512
%i17 = load i64, ptr %i16, align 8
%i18 = and i64 %i15, 4294967295
%i19 = add i64 %i15, %i17
%i20 = shl i64 %i17, 1
%i21 = and i64 %i20, 8589934590
%i22 = mul i64 %i21, %i18
%i23 = add i64 %i19, %i22
%i24 = xor i64 %i23, %i5
%i25 = tail call i64 @llvm.fshl.i64(i64 %i24, i64 %i24, i64 40)
%i26 = and i64 %i25, 4294967295
%i27 = add i64 %i25, %i11
%i28 = shl i64 %i11, 1
%i29 = and i64 %i28, 8589934590
%i30 = mul i64 %i26, %i29
%i31 = add i64 %i27, %i30
%i32 = xor i64 %i31, %i15
%i33 = tail call i64 @llvm.fshl.i64(i64 %i32, i64 %i32, i64 48)
%i34 = and i64 %i33, 4294967295
%i35 = add i64 %i33, %i23
%i36 = shl i64 %i23, 1
%i37 = and i64 %i36, 8589934590
%i38 = mul i64 %i34, %i37
%i39 = add i64 %i35, %i38
%i40 = xor i64 %i39, %i25
%i41 = tail call i64 @llvm.fshl.i64(i64 %i40, i64 %i40, i64 1)
%i42 = getelementptr i8, ptr %i2, i32 8
%i43 = load i64, ptr %i42, align 8
%i44 = getelementptr i8, ptr %i2, i32 264
%i45 = load i64, ptr %i44, align 8
%i46 = and i64 %i45, 4294967295
%i47 = add i64 %i45, %i43
%i48 = shl i64 %i43, 1
%i49 = and i64 %i48, 8589934590
%i50 = mul i64 %i49, %i46
%i51 = add i64 %i47, %i50
%i52 = getelementptr i8, ptr %i2, i32 776
%i53 = load i64, ptr %i52, align 8
%i54 = xor i64 %i51, %i53
%i55 = tail call i64 @llvm.fshl.i64(i64 %i54, i64 %i54, i64 32)
%i56 = getelementptr i8, ptr %i2, i32 520
%i57 = load i64, ptr %i56, align 8
%i58 = and i64 %i55, 4294967295
%i59 = add i64 %i55, %i57
%i60 = shl i64 %i57, 1
%i61 = and i64 %i60, 8589934590
%i62 = mul i64 %i61, %i58
%i63 = add i64 %i59, %i62
%i64 = xor i64 %i63, %i45
%i65 = tail call i64 @llvm.fshl.i64(i64 %i64, i64 %i64, i64 40)
%i66 = and i64 %i65, 4294967295
%i67 = add i64 %i65, %i51
%i68 = shl i64 %i51, 1
%i69 = and i64 %i68, 8589934590
%i70 = mul i64 %i66, %i69
%i71 = add i64 %i67, %i70
%i72 = xor i64 %i71, %i55
%i73 = tail call i64 @llvm.fshl.i64(i64 %i72, i64 %i72, i64 48)
%i74 = and i64 %i73, 4294967295
%i75 = add i64 %i73, %i63
%i76 = shl i64 %i63, 1
%i77 = and i64 %i76, 8589934590
%i78 = mul i64 %i74, %i77
%i79 = add i64 %i75, %i78
%i80 = xor i64 %i79, %i65
%i81 = tail call i64 @llvm.fshl.i64(i64 %i80, i64 %i80, i64 1)
%i82 = getelementptr i8, ptr %i2, i32 128
%i83 = load i64, ptr %i82, align 8
%i84 = getelementptr i8, ptr %i2, i32 384
%i85 = load i64, ptr %i84, align 8
%i86 = and i64 %i85, 4294967295
%i87 = add i64 %i85, %i83
%i88 = shl i64 %i83, 1
%i89 = and i64 %i88, 8589934590
%i90 = mul i64 %i89, %i86
%i91 = add i64 %i87, %i90
%i92 = getelementptr i8, ptr %i2, i32 896
%i93 = load i64, ptr %i92, align 8
%i94 = xor i64 %i91, %i93
%i95 = tail call i64 @llvm.fshl.i64(i64 %i94, i64 %i94, i64 32)
%i96 = getelementptr i8, ptr %i2, i32 640
%i97 = load i64, ptr %i96, align 8
%i98 = and i64 %i95, 4294967295
%i99 = add i64 %i95, %i97
%i100 = shl i64 %i97, 1
%i101 = and i64 %i100, 8589934590
%i102 = mul i64 %i101, %i98
%i103 = add i64 %i99, %i102
%i104 = xor i64 %i103, %i85
%i105 = tail call i64 @llvm.fshl.i64(i64 %i104, i64 %i104, i64 40)
%i106 = and i64 %i105, 4294967295
%i107 = add i64 %i105, %i91
%i108 = shl i64 %i91, 1
%i109 = and i64 %i108, 8589934590
%i110 = mul i64 %i106, %i109
%i111 = add i64 %i107, %i110
%i112 = xor i64 %i111, %i95
%i113 = tail call i64 @llvm.fshl.i64(i64 %i112, i64 %i112, i64 48)
%i114 = and i64 %i113, 4294967295
%i115 = add i64 %i113, %i103
%i116 = shl i64 %i103, 1
%i117 = and i64 %i116, 8589934590
%i118 = mul i64 %i114, %i117
%i119 = add i64 %i115, %i118
%i120 = xor i64 %i119, %i105
%i121 = tail call i64 @llvm.fshl.i64(i64 %i120, i64 %i120, i64 1)
%i122 = getelementptr i8, ptr %i2, i32 136
%i123 = load i64, ptr %i122, align 8
%i124 = getelementptr i8, ptr %i2, i32 392
%i125 = load i64, ptr %i124, align 8
%i126 = and i64 %i125, 4294967295
%i127 = add i64 %i125, %i123
%i128 = shl i64 %i123, 1
%i129 = and i64 %i128, 8589934590
%i130 = mul i64 %i129, %i126
%i131 = add i64 %i127, %i130
%i132 = getelementptr i8, ptr %i2, i32 904
%i133 = load i64, ptr %i132, align 8
%i134 = xor i64 %i131, %i133
%i135 = tail call i64 @llvm.fshl.i64(i64 %i134, i64 %i134, i64 32)
%i136 = getelementptr i8, ptr %i2, i32 648
%i137 = load i64, ptr %i136, align 8
%i138 = and i64 %i135, 4294967295
%i139 = add i64 %i135, %i137
%i140 = shl i64 %i137, 1
%i141 = and i64 %i140, 8589934590
%i142 = mul i64 %i141, %i138
%i143 = add i64 %i139, %i142
%i144 = xor i64 %i143, %i125
%i145 = tail call i64 @llvm.fshl.i64(i64 %i144, i64 %i144, i64 40)
%i146 = and i64 %i145, 4294967295
%i147 = add i64 %i145, %i131
%i148 = shl i64 %i131, 1
%i149 = and i64 %i148, 8589934590
%i150 = mul i64 %i146, %i149
%i151 = add i64 %i147, %i150
%i152 = xor i64 %i151, %i135
%i153 = tail call i64 @llvm.fshl.i64(i64 %i152, i64 %i152, i64 48)
%i154 = and i64 %i153, 4294967295
%i155 = add i64 %i153, %i143
%i156 = shl i64 %i143, 1
%i157 = and i64 %i156, 8589934590
%i158 = mul i64 %i154, %i157
%i159 = add i64 %i155, %i158
%i160 = xor i64 %i159, %i145
%i161 = tail call i64 @llvm.fshl.i64(i64 %i160, i64 %i160, i64 1)
%i162 = and i64 %i81, 4294967295
%i163 = add i64 %i81, %i31
%i164 = shl i64 %i31, 1
%i165 = and i64 %i164, 8589934590
%i166 = mul i64 %i162, %i165
%i167 = add i64 %i163, %i166
%i168 = xor i64 %i153, %i167
%i169 = tail call i64 @llvm.fshl.i64(i64 %i168, i64 %i168, i64 32)
%i170 = and i64 %i169, 4294967295
%i171 = add i64 %i169, %i119
%i172 = shl i64 %i119, 1
%i173 = and i64 %i172, 8589934590
%i174 = mul i64 %i170, %i173
%i175 = add i64 %i171, %i174
%i176 = xor i64 %i175, %i81
%i177 = tail call i64 @llvm.fshl.i64(i64 %i176, i64 %i176, i64 40)
%i178 = and i64 %i177, 4294967295
%i179 = add i64 %i177, %i167
%i180 = shl i64 %i167, 1
%i181 = and i64 %i180, 8589934590
%i182 = mul i64 %i178, %i181
%i183 = add i64 %i179, %i182
store i64 %i183, ptr %i2, align 8
%i184 = xor i64 %i183, %i169
%i185 = tail call i64 @llvm.fshl.i64(i64 %i184, i64 %i184, i64 48)
store i64 %i185, ptr %i132, align 8
%i186 = and i64 %i185, 4294967295
%i187 = add i64 %i185, %i175
%i188 = shl i64 %i175, 1
%i189 = and i64 %i188, 8589934590
%i190 = mul i64 %i186, %i189
%i191 = add i64 %i187, %i190
store i64 %i191, ptr %i96, align 8
%i192 = xor i64 %i191, %i177
%i193 = tail call i64 @llvm.fshl.i64(i64 %i192, i64 %i192, i64 1)
store i64 %i193, ptr %i44, align 8
%i194 = and i64 %i121, 4294967295
%i195 = add i64 %i121, %i71
%i196 = shl i64 %i71, 1
%i197 = and i64 %i196, 8589934590
%i198 = mul i64 %i194, %i197
%i199 = add i64 %i195, %i198
%i200 = xor i64 %i199, %i33
%i201 = tail call i64 @llvm.fshl.i64(i64 %i200, i64 %i200, i64 32)
%i202 = and i64 %i201, 4294967295
%i203 = add i64 %i159, %i201
%i204 = shl i64 %i159, 1
%i205 = and i64 %i204, 8589934590
%i206 = mul i64 %i205, %i202
%i207 = add i64 %i203, %i206
%i208 = xor i64 %i207, %i121
%i209 = tail call i64 @llvm.fshl.i64(i64 %i208, i64 %i208, i64 40)
%i210 = and i64 %i209, 4294967295
%i211 = add i64 %i209, %i199
%i212 = shl i64 %i199, 1
%i213 = and i64 %i212, 8589934590
%i214 = mul i64 %i210, %i213
%i215 = add i64 %i211, %i214
store i64 %i215, ptr %i42, align 8
%i216 = xor i64 %i215, %i201
%i217 = tail call i64 @llvm.fshl.i64(i64 %i216, i64 %i216, i64 48)
store i64 %i217, ptr %i12, align 8
%i218 = and i64 %i217, 4294967295
%i219 = add i64 %i217, %i207
%i220 = shl i64 %i207, 1
%i221 = and i64 %i220, 8589934590
%i222 = mul i64 %i218, %i221
%i223 = add i64 %i219, %i222
store i64 %i223, ptr %i136, align 8
%i224 = xor i64 %i223, %i209
%i225 = tail call i64 @llvm.fshl.i64(i64 %i224, i64 %i224, i64 1)
store i64 %i225, ptr %i84, align 8
%i226 = and i64 %i161, 4294967295
%i227 = add i64 %i161, %i111
%i228 = shl i64 %i111, 1
%i229 = and i64 %i228, 8589934590
%i230 = mul i64 %i226, %i229
%i231 = add i64 %i227, %i230
%i232 = xor i64 %i231, %i73
%i233 = tail call i64 @llvm.fshl.i64(i64 %i232, i64 %i232, i64 32)
%i234 = and i64 %i233, 4294967295
%i235 = add i64 %i233, %i39
%i236 = shl i64 %i39, 1
%i237 = and i64 %i236, 8589934590
%i238 = mul i64 %i234, %i237
%i239 = add i64 %i235, %i238
%i240 = xor i64 %i239, %i161
%i241 = tail call i64 @llvm.fshl.i64(i64 %i240, i64 %i240, i64 40)
%i242 = and i64 %i241, 4294967295
%i243 = add i64 %i241, %i231
%i244 = shl i64 %i231, 1
%i245 = and i64 %i244, 8589934590
%i246 = mul i64 %i242, %i245
%i247 = add i64 %i243, %i246
store i64 %i247, ptr %i82, align 8
%i248 = xor i64 %i247, %i233
%i249 = tail call i64 @llvm.fshl.i64(i64 %i248, i64 %i248, i64 48)
store i64 %i249, ptr %i52, align 8
%i250 = and i64 %i249, 4294967295
%i251 = add i64 %i249, %i239
%i252 = shl i64 %i239, 1
%i253 = and i64 %i252, 8589934590
%i254 = mul i64 %i250, %i253
%i255 = add i64 %i251, %i254
store i64 %i255, ptr %i16, align 8
%i256 = xor i64 %i255, %i241
%i257 = tail call i64 @llvm.fshl.i64(i64 %i256, i64 %i256, i64 1)
store i64 %i257, ptr %i124, align 8
%i258 = and i64 %i41, 4294967295
%i259 = add i64 %i151, %i41
%i260 = shl i64 %i151, 1
%i261 = and i64 %i260, 8589934590
%i262 = mul i64 %i261, %i258
%i263 = add i64 %i259, %i262
%i264 = xor i64 %i263, %i113
%i265 = tail call i64 @llvm.fshl.i64(i64 %i264, i64 %i264, i64 32)
%i266 = and i64 %i265, 4294967295
%i267 = add i64 %i265, %i79
%i268 = shl i64 %i79, 1
%i269 = and i64 %i268, 8589934590
%i270 = mul i64 %i266, %i269
%i271 = add i64 %i267, %i270
%i272 = xor i64 %i271, %i41
%i273 = tail call i64 @llvm.fshl.i64(i64 %i272, i64 %i272, i64 40)
%i274 = and i64 %i273, 4294967295
%i275 = add i64 %i273, %i263
%i276 = shl i64 %i263, 1
%i277 = and i64 %i276, 8589934590
%i278 = mul i64 %i274, %i277
%i279 = add i64 %i275, %i278
store i64 %i279, ptr %i122, align 8
%i280 = xor i64 %i279, %i265
%i281 = tail call i64 @llvm.fshl.i64(i64 %i280, i64 %i280, i64 48)
store i64 %i281, ptr %i92, align 8
%i282 = and i64 %i281, 4294967295
%i283 = add i64 %i281, %i271
%i284 = shl i64 %i271, 1
%i285 = and i64 %i284, 8589934590
%i286 = mul i64 %i282, %i285
%i287 = add i64 %i283, %i286
store i64 %i287, ptr %i56, align 8
%i288 = xor i64 %i287, %i273
%i289 = tail call i64 @llvm.fshl.i64(i64 %i288, i64 %i288, i64 1)
store i64 %i289, ptr %i4, align 8
%i290 = add nuw nsw i32 %i, 1
%i291 = icmp eq i32 %i290, 8
br i1 %i291, label %.exitStub, label %bb
.exitStub: ; preds = %bb
ret void
}
declare i64 @llvm.fshl.i64(i64, i64, i64)
;.
; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
;.