llvm/test/Transforms/LoopVectorize/VPlan/simplify-reverse-reverse.ll

; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --filter-out-after "middle.block:" --version 6
; RUN: opt -p loop-vectorize -force-vector-width=4 -disable-output -vplan-print-after=simplifyReverses %s 2>&1 | FileCheck %s

define void @reverse_copy(ptr noalias %src, ptr noalias %dst, i32 %n) {
; CHECK-LABEL: VPlan for loop in 'reverse_copy'
; CHECK:  VPlan 'Initial VPlan for VF={4},UF>=1' {
; CHECK-NEXT:  Live-in vp<[[VP0:%[0-9]+]]> = VF
; CHECK-NEXT:  Live-in vp<[[VP1:%[0-9]+]]> = VF * UF
; CHECK-NEXT:  Live-in vp<[[VP2:%[0-9]+]]> = vector-trip-count
; CHECK-NEXT:  vp<[[VP3:%[0-9]+]]> = original trip-count
; CHECK-EMPTY:
; CHECK-NEXT:  ir-bb<entry>:
; CHECK-NEXT:    EMIT vp<[[VP3]]> = EXPAND SCEV ((-1 * (0 smin (-1 + %n)<nsw>)) + %n)
; CHECK-NEXT:  Successor(s): scalar.ph, vector.ph
; CHECK-EMPTY:
; CHECK-NEXT:  vector.ph:
; CHECK-NEXT:    vp<[[VP4:%[0-9]+]]> = DERIVED-IV ir<%n> + vp<[[VP2]]> * ir<-1>
; CHECK-NEXT:  Successor(s): vector loop
; CHECK-EMPTY:
; CHECK-NEXT:  <x1> vector loop: {
; CHECK-NEXT:  vp<[[VP5:%[0-9]+]]> = CANONICAL-IV
; CHECK-EMPTY:
; CHECK-NEXT:    vector.body:
; CHECK-NEXT:      ir<%iv> = WIDEN-INDUCTION nsw ir<%n>, ir<-1>, vp<[[VP0]]>
; CHECK-NEXT:      vp<[[VP6:%[0-9]+]]> = DERIVED-IV ir<%n> + vp<[[VP5]]> * ir<-1>
; CHECK-NEXT:      vp<[[VP7:%[0-9]+]]> = SCALAR-STEPS vp<[[VP6]]>, ir<-1>, vp<[[VP0]]>
; CHECK-NEXT:      CLONE ir<%iv.next> = add nsw vp<[[VP7]]>, ir<-1>
; CHECK-NEXT:      CLONE ir<%gep.src> = getelementptr ir<%src>, ir<%iv.next>
; CHECK-NEXT:      vp<[[VP8:%[0-9]+]]> = vector-end-pointer i32, ir<%gep.src>, vp<[[VP0]]>
; CHECK-NEXT:      WIDEN ir<%x> = load vp<[[VP8]]>
; CHECK-NEXT:      EMIT vp<[[VP9:%[0-9]+]]> = reverse ir<%x>
; CHECK-NEXT:      CLONE ir<%gep.dst> = getelementptr ir<%dst>, ir<%iv.next>
; CHECK-NEXT:      vp<[[VP10:%[0-9]+]]> = vector-end-pointer i32, ir<%gep.dst>, vp<[[VP0]]>
; CHECK-NEXT:      EMIT vp<[[VP11:%[0-9]+]]> = reverse vp<[[VP9]]>
; CHECK-NEXT:      WIDEN store vp<[[VP10]]>, ir<%x>
; CHECK-NEXT:      EMIT vp<%index.next> = add nuw vp<[[VP5]]>, vp<[[VP1]]>
; CHECK-NEXT:      EMIT branch-on-count vp<%index.next>, vp<[[VP2]]>
; CHECK-NEXT:    No successors
; CHECK-NEXT:  }
; CHECK-NEXT:  Successor(s): middle.block
; CHECK-EMPTY:
; CHECK-NEXT:  middle.block:
;
entry:
  br label %loop

loop:
  %iv = phi i32 [%n, %entry], [%iv.next, %loop]
  %iv.next = add nsw i32 %iv, -1
  %gep.src = getelementptr i32, ptr %src, i32 %iv.next
  %x = load i32, ptr %gep.src
  %gep.dst = getelementptr i32, ptr %dst, i32 %iv.next
  store i32 %x, ptr %gep.dst
  %ec = icmp sgt i32 %iv.next, 0
  br i1 %ec, label %loop, label %exit

exit:
  ret void
}