llvm/test/CodeGen/X86/vec-2bit-int.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s

define dso_local <2 x i2> @foo(<2 x i2> %v1, <2 x i2> %v2) {
; CHECK-LABEL: foo:
; CHECK:       # %bb.0: # %entry
; CHECK-NEXT:    movq %xmm1, %rax
; CHECK-NEXT:    andb $3, %al
; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm1[2,3,2,3]
; CHECK-NEXT:    movq %xmm2, %rcx
; CHECK-NEXT:    shlb $2, %cl
; CHECK-NEXT:    orb %al, %cl
; CHECK-NEXT:    andb $15, %cl
; CHECK-NEXT:    movb %cl, -{{[0-9]+}}(%rsp)
; CHECK-NEXT:    movq %xmm0, %rax
; CHECK-NEXT:    andb $3, %al
; CHECK-NEXT:    pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3]
; CHECK-NEXT:    movq %xmm2, %rcx
; CHECK-NEXT:    shlb $2, %cl
; CHECK-NEXT:    orb %al, %cl
; CHECK-NEXT:    andb $15, %cl
; CHECK-NEXT:    movb %cl, -{{[0-9]+}}(%rsp)
; CHECK-NEXT:    paddq %xmm1, %xmm0
; CHECK-NEXT:    retq
 entry:
   %v2.addr = alloca <2 x i2>, align 2
   %v1.addr = alloca <2 x i2>, align 2
   store <2 x i2> %v2, ptr %v2.addr, align 2
   store <2 x i2> %v1, ptr %v1.addr, align 2
   %0 = load <2 x i2>, ptr %v1.addr, align 2
   %1 = load <2 x i2>, ptr %v2.addr, align 2
   %add = add <2 x i2> %0, %1
   ret <2 x i2> %add
}