llvm/test/CodeGen/AMDGPU/code-size-estimate.mir

# RUN: llc -mtriple=amdgcn--amdpal --start-after=greedy -mcpu=gfx90a -show-mc-encoding  -o - %s | FileCheck %s
# RUN: llc -mtriple=amdgcn--amdpal --start-after=greedy -mcpu=gfx802 -show-mc-encoding  -o - %s | FileCheck %s


# CHECK: indirect_mov:                           ; @indirect_mov
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: v_mov_b32_e32 v16, v1                   ; encoding: [0x01,0x03,0x20,0x7e]
# CHECK: v_mov_b32_e32 v0, v3                    ; encoding: [0x03,0x03,0x00,0x7e]
# CHECK: ; codeLenInByte = 12

---
name:            indirect_mov
tracksRegLiveness: true
body:             |
  bb.0:
  liveins: $vgpr1, $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15

  $vgpr16 = V_MOV_B32_indirect_read undef $vgpr1, implicit $exec, implicit $m0, implicit $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10_vgpr11_vgpr12_vgpr13_vgpr14_vgpr15
  V_MOV_B32_indirect_write undef $vgpr0, undef $vgpr3, implicit $exec, implicit $m0, implicit-def $vgpr0_vgpr1_vgpr2_vgpr3, implicit killed $vgpr0_vgpr1_vgpr2_vgpr3(tied-def 4)
...

# CHECK: meta:                                   ; @meta
# CHECK: ; wave barrier
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: ; codeLenInByte = 4
---
name:            meta
tracksRegLiveness: true
body:             |
  bb.0:

  WAVE_BARRIER
...

# CHECK: align4:                                 ; @align4
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: s_cbranch_scc1 .LBB{{[0-9_]+}}          ; encoding: [A,A,0x85,0xbf]
# CHECK: s_barrier                               ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align        2
# CHECK: s_endpgm                                ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 16

---
name:            align4
tracksRegLiveness: true
body:             |
  bb.0:
    $scc = IMPLICIT_DEF
    S_CBRANCH_SCC1 %bb.2, implicit $scc

  bb.1:
    S_BARRIER

  bb.2 (align 4):
    S_ENDPGM 0
...

# CHECK: align8:                                 ; @align8
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: s_cbranch_scc1 .LBB{{[0-9_]+}}          ; encoding: [A,A,0x85,0xbf]
# CHECK: s_barrier                               ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align        3
# CHECK: s_endpgm                                ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 20
---
name:            align8
tracksRegLiveness: true
body:             |
  bb.0:
    $scc = IMPLICIT_DEF
    S_CBRANCH_SCC1 %bb.2, implicit $scc

  bb.1:
    S_BARRIER

  bb.2 (align 8):
    S_ENDPGM 0
...

# CHECK: align16:                                ; @align16
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: s_cbranch_scc1 .LBB{{[0-9_]+}}          ; encoding: [A,A,0x85,0xbf]
# CHECK: s_barrier                               ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align        4
# CHECK: s_endpgm                                ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 20
---
name:            align16
tracksRegLiveness: true
body:             |
  bb.0:
    $scc = IMPLICIT_DEF
    S_CBRANCH_SCC1 %bb.2, implicit $scc

  bb.1:
    S_BARRIER

  bb.2 (align 16):
    S_ENDPGM 0
...

# CHECK: align32:                                ; @align32
# CHECK: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; encoding: [0x00,0x00,0x8c,0xbf]
# CHECK: s_cbranch_scc1 .LBB{{[0-9_]+}}          ; encoding: [A,A,0x85,0xbf]
# CHECK: s_barrier                               ; encoding: [0x00,0x00,0x8a,0xbf]
# CHECK: .p2align        5
# CHECK: s_endpgm                                ; encoding: [0x00,0x00,0x81,0xbf]
# CHECK: ; codeLenInByte = 36
---
name:            align32
tracksRegLiveness: true
body:             |
  bb.0:
    $scc = IMPLICIT_DEF
    S_CBRANCH_SCC1 %bb.2, implicit $scc

  bb.1:
    S_BARRIER

  bb.2 (align 32):
    S_ENDPGM 0
...