llvm/test/CodeGen/AMDGPU/attributor-loop-issue-58639.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
; RUN: opt -S -mtriple=amdgcn-amd-amdhsa -passes=amdgpu-attributor %s | FileCheck %s

%0 = type { ptr, ptr }

define internal fastcc i1 @widget(ptr %arg) {
; CHECK-LABEL: define {{[^@]+}}@widget
; CHECK-SAME: (ptr [[ARG:%.*]]) #[[ATTR0:[0-9]+]] {
; CHECK-NEXT:  bb:
; CHECK-NEXT:    [[TMP:%.*]] = getelementptr inbounds [[TMP0:%.*]], ptr [[ARG]], i64 0, i32 1
; CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[TMP]], align 8
; CHECK-NEXT:    [[TMP2:%.*]] = call fastcc double @baz(ptr [[TMP1]])
; CHECK-NEXT:    ret i1 false
;
bb:
  %tmp = getelementptr inbounds %0, ptr %arg, i64 0, i32 1
  %tmp1 = load ptr, ptr %tmp, align 8
  %tmp2 = call fastcc double @baz(ptr %tmp1)
  ret i1 false
}

define internal fastcc double @baz(ptr %arg) {
; CHECK-LABEL: define {{[^@]+}}@baz
; CHECK-SAME: (ptr [[ARG:%.*]]) #[[ATTR0]] {
; CHECK-NEXT:  bb:
; CHECK-NEXT:    [[TMP1:%.*]] = load ptr, ptr [[ARG]], align 8
; CHECK-NEXT:    [[TMP2:%.*]] = tail call double [[TMP1]]()
; CHECK-NEXT:    br label [[BB3:%.*]]
; CHECK:       bb3:
; CHECK-NEXT:    [[TMP4:%.*]] = getelementptr inbounds [[TMP0:%.*]], ptr [[ARG]], i64 0, i32 1
; CHECK-NEXT:    br label [[BB5:%.*]]
; CHECK:       bb5:
; CHECK-NEXT:    [[TMP6:%.*]] = load ptr, ptr [[TMP4]], align 8
; CHECK-NEXT:    [[TMP7:%.*]] = call fastcc i1 @widget(ptr [[TMP6]])
; CHECK-NEXT:    br label [[BB5]]
;
bb:
  %tmp1 = load ptr, ptr %arg, align 8
  %tmp2 = tail call double %tmp1()
  br label %bb3

bb3:                                              ; preds = %bb
  %tmp4 = getelementptr inbounds %0, ptr %arg, i64 0, i32 1
  br label %bb5

bb5:                                              ; preds = %bb5, %bb3
  %tmp6 = load ptr, ptr %tmp4, align 8
  %tmp7 = call fastcc i1 @widget(ptr %tmp6)
  br label %bb5
}

define amdgpu_kernel void @entry() {
; CHECK-LABEL: define {{[^@]+}}@entry
; CHECK-SAME: () #[[ATTR0]] {
; CHECK-NEXT:    [[ALLOCA:%.*]] = alloca [[TMP0:%.*]], align 8, addrspace(5)
; CHECK-NEXT:    [[CAST:%.*]] = addrspacecast ptr addrspace(5) [[ALLOCA]] to ptr
; CHECK-NEXT:    [[ARST:%.*]] = call double @baz(ptr [[CAST]])
; CHECK-NEXT:    ret void
;
  %alloca = alloca %0, align 8, addrspace(5)
  %cast = addrspacecast ptr addrspace(5) %alloca to ptr
  %arst = call double @baz(ptr %cast)
  ret void
}
;.
; CHECK: attributes #[[ATTR0]] = { "amdgpu-waves-per-eu"="4,10" "uniform-work-group-size"="false" }
;.