| // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --function-signature --include-generated-funcs --replace-value-regex "__omp_offloading_[0-9a-z]+_[0-9a-z]+" "reduction_size[.].+[.]" "pl_cond[.].+[.|,]" --prefix-filecheck-ir-name _ |
| // expected-no-diagnostics |
| #ifndef HEADER |
| #define HEADER |
| // Test host codegen. |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK1 |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK2 |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK3 |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --check-prefix=CHECK4 |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK5 |
| |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| // Test target codegen - host bc file has to be created first. (no significant differences with host version of target region) |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --check-prefix=CHECK10 |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK11 |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --check-prefix=CHECK12 |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --check-prefix=CHECK13 |
| |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm-bc %s -o %t-ppc-host.bc |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple powerpc64le-unknown-unknown -fopenmp-targets=powerpc64le-ibm-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-ppc-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm-bc %s -o %t-x86-host.bc |
| // RUN: %clang_cc1 -DCK1 -verify -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-llvm %s -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -std=c++11 -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -emit-pch -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -o %t %s |
| // RUN: %clang_cc1 -DCK1 -fopenmp-simd -x c++ -triple i386-unknown-unknown -fopenmp-targets=i386-pc-linux-gnu -std=c++11 -fopenmp-is-device -fopenmp-host-ir-file-path %t-x86-host.bc -include-pch %t -verify %s -emit-llvm -o - | FileCheck %s --implicit-check-not="{{__kmpc|__tgt}}" |
| |
| #ifdef CK1 |
| |
| |
| int target_teams_fun(int *g){ |
| int n = 1000; |
| int a[1000]; |
| int te = n / 128; |
| int th = 128; |
| // discard n_addr |
| // discard capture expressions for te and th |
| |
| #pragma omp target teams distribute parallel for num_teams(te), thread_limit(th) |
| for(int i = 0; i < n; i++) { |
| a[i] = 0; |
| #pragma omp cancel for |
| } |
| |
| {{{ |
| #pragma omp target teams distribute parallel for is_device_ptr(g) |
| for(int i = 0; i < n; i++) { |
| a[i] = g[0]; |
| } |
| }}} |
| |
| // outlined target regions |
| |
| |
| |
| |
| return a[0]; |
| } |
| |
| #endif // CK1 |
| #endif // HEADER |
| // CHECK1-LABEL: define {{[^@]+}}@_Z16target_teams_funPi |
| // CHECK1-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[N:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 |
| // CHECK1-NEXT: [[TE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TH:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[N_CASTED5:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: store i32 1000, i32* [[N]], align 4 |
| // CHECK1-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 |
| // CHECK1-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 |
| // CHECK1-NEXT: store i32 128, i32* [[TH]], align 4 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP5]], i32* [[CONV2]], align 4 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED3]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP7]], i32* [[CONV4]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED3]], align 8 |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51(i64 [[TMP4]], [1000 x i32]* [[A]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED5]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP9]], i32* [[CONV6]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i64, i64* [[N_CASTED5]], align 8 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i64 [[TMP10]], [1000 x i32]* [[A]], i32* [[TMP11]]) #[[ATTR2]] |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: ret i32 [[TMP12]] |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) |
| // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* |
| // CHECK1-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 |
| // CHECK1-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK1: omp.precond.then: |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) |
| // CHECK1-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK1: omp.precond.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK1: omp.precond.then: |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK1-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK1-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK1-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK1-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK1: .cancel.exit: |
| // CHECK1-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK1: .cancel.continue: |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK1-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK1-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK1: cancel.exit: |
| // CHECK1-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK1-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK1: omp.precond.end: |
| // CHECK1-NEXT: br label [[CANCEL_CONT]] |
| // CHECK1: cancel.cont: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK1-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK1: omp.precond.then: |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK1-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK1-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK1-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK1-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK1-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK1: omp.precond.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK1-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK1-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK1-NEXT: entry: |
| // CHECK1-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK1-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK1-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK1-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK1-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK1-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK1-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK1-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK1-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK1-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK1-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK1-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK1-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK1-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK1-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK1: omp.precond.then: |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK1-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK1-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK1-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK1-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK1-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK1-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK1-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK1: cond.true: |
| // CHECK1-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK1-NEXT: br label [[COND_END:%.*]] |
| // CHECK1: cond.false: |
| // CHECK1-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: br label [[COND_END]] |
| // CHECK1: cond.end: |
| // CHECK1-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK1-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK1-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK1: omp.inner.for.cond: |
| // CHECK1-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK1-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK1-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK1: omp.inner.for.body: |
| // CHECK1-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK1-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK1-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK1-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK1-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 |
| // CHECK1-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK1-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK1-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK1-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK1-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 |
| // CHECK1-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK1: omp.body.continue: |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK1: omp.inner.for.inc: |
| // CHECK1-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK1-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK1-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK1: omp.inner.for.end: |
| // CHECK1-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK1: omp.loop.exit: |
| // CHECK1-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK1-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK1-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK1-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK1: omp.precond.end: |
| // CHECK1-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@_Z16target_teams_funPi |
| // CHECK2-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[N:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 |
| // CHECK2-NEXT: [[TE:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TH:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[N_CASTED9:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_BASEPTRS11:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_PTRS12:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK2-NEXT: [[DOTOFFLOAD_MAPPERS13:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK2-NEXT: [[_TMP14:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: store i32 1000, i32* [[N]], align 4 |
| // CHECK2-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 |
| // CHECK2-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 |
| // CHECK2-NEXT: store i32 128, i32* [[TH]], align 4 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP5]], i32* [[CONV2]], align 4 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED3]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP7]], i32* [[CONV4]], align 4 |
| // CHECK2-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED3]], align 8 |
| // CHECK2-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 |
| // CHECK2-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 |
| // CHECK2-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP13]], align 8 |
| // CHECK2-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [1000 x i32]** |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP15]], align 8 |
| // CHECK2-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [1000 x i32]** |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP17]], align 8 |
| // CHECK2-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP18]], align 8 |
| // CHECK2-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK2-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP20]], align 8 |
| // CHECK2-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK2-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP6]], i64* [[TMP22]], align 8 |
| // CHECK2-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP23]], align 8 |
| // CHECK2-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK2-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP25]], align 8 |
| // CHECK2-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK2-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP8]], i64* [[TMP27]], align 8 |
| // CHECK2-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP28]], align 8 |
| // CHECK2-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP30:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR_5]], align 4 |
| // CHECK2-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 |
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP34]], 0 |
| // CHECK2-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK2-NEXT: [[SUB8:%.*]] = sub nsw i32 [[DIV7]], 1 |
| // CHECK2-NEXT: store i32 [[SUB8]], i32* [[DOTCAPTURE_EXPR_6]], align 4 |
| // CHECK2-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_6]], align 4 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP35]], 1 |
| // CHECK2-NEXT: [[TMP36:%.*]] = zext i32 [[ADD]] to i64 |
| // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP36]]) |
| // CHECK2-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.region_id, i32 4, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP31]], i32 [[TMP32]]) |
| // CHECK2-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 |
| // CHECK2-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK2: omp_offload.failed: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51(i64 [[TMP4]], [1000 x i32]* [[A]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK2: omp_offload.cont: |
| // CHECK2-NEXT: [[TMP39:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK2-NEXT: [[CONV10:%.*]] = bitcast i64* [[N_CASTED9]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP39]], i32* [[CONV10]], align 4 |
| // CHECK2-NEXT: [[TMP40:%.*]] = load i64, i64* [[N_CASTED9]], align 8 |
| // CHECK2-NEXT: [[TMP41:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP40]], i64* [[TMP43]], align 8 |
| // CHECK2-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* |
| // CHECK2-NEXT: store i64 [[TMP40]], i64* [[TMP45]], align 8 |
| // CHECK2-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 0 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP46]], align 8 |
| // CHECK2-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [1000 x i32]** |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP48]], align 8 |
| // CHECK2-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 1 |
| // CHECK2-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [1000 x i32]** |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP50]], align 8 |
| // CHECK2-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 1 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP51]], align 8 |
| // CHECK2-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 2 |
| // CHECK2-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32** |
| // CHECK2-NEXT: store i32* [[TMP41]], i32** [[TMP53]], align 8 |
| // CHECK2-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 2 |
| // CHECK2-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32** |
| // CHECK2-NEXT: store i32* [[TMP41]], i32** [[TMP55]], align 8 |
| // CHECK2-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 2 |
| // CHECK2-NEXT: store i8* null, i8** [[TMP56]], align 8 |
| // CHECK2-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 |
| // CHECK2-NEXT: [[TMP59:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_15]], align 4 |
| // CHECK2-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_15]], align 4 |
| // CHECK2-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP60]], 0 |
| // CHECK2-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 |
| // CHECK2-NEXT: [[SUB19:%.*]] = sub nsw i32 [[DIV18]], 1 |
| // CHECK2-NEXT: store i32 [[SUB19]], i32* [[DOTCAPTURE_EXPR_16]], align 4 |
| // CHECK2-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 |
| // CHECK2-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP61]], 1 |
| // CHECK2-NEXT: [[TMP62:%.*]] = zext i32 [[ADD20]] to i64 |
| // CHECK2-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP62]]) |
| // CHECK2-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.region_id, i32 3, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK2-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 |
| // CHECK2-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED21:%.*]], label [[OMP_OFFLOAD_CONT22:%.*]] |
| // CHECK2: omp_offload.failed21: |
| // CHECK2-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i64 [[TMP40]], [1000 x i32]* [[A]], i32* [[TMP41]]) #[[ATTR2]] |
| // CHECK2-NEXT: br label [[OMP_OFFLOAD_CONT22]] |
| // CHECK2: omp_offload.cont22: |
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 |
| // CHECK2-NEXT: [[TMP65:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK2-NEXT: ret i32 [[TMP65]] |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) |
| // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* |
| // CHECK2-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 |
| // CHECK2-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK2: omp.precond.then: |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK2: cond.true: |
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: br label [[COND_END:%.*]] |
| // CHECK2: cond.false: |
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: br label [[COND_END]] |
| // CHECK2: cond.end: |
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK2: omp.inner.for.cond: |
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK2: omp.inner.for.body: |
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK2: omp.inner.for.inc: |
| // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK2: omp.inner.for.end: |
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK2: omp.loop.exit: |
| // CHECK2-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) |
| // CHECK2-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK2: omp.precond.end: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK2: omp.precond.then: |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK2-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK2: cond.true: |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: br label [[COND_END:%.*]] |
| // CHECK2: cond.false: |
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: br label [[COND_END]] |
| // CHECK2: cond.end: |
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK2: omp.inner.for.cond: |
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK2: omp.inner.for.body: |
| // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK2-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 |
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK2-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK2-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK2-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK2-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK2-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK2: .cancel.exit: |
| // CHECK2-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK2: .cancel.continue: |
| // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK2: omp.body.continue: |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK2: omp.inner.for.inc: |
| // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK2-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK2: omp.inner.for.end: |
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK2: omp.loop.exit: |
| // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK2-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK2: cancel.exit: |
| // CHECK2-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK2-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK2: omp.precond.end: |
| // CHECK2-NEXT: br label [[CANCEL_CONT]] |
| // CHECK2: cancel.cont: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK2-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK2: omp.precond.then: |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK2-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK2-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK2: cond.true: |
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: br label [[COND_END:%.*]] |
| // CHECK2: cond.false: |
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: br label [[COND_END]] |
| // CHECK2: cond.end: |
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK2: omp.inner.for.cond: |
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK2-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK2: omp.inner.for.body: |
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK2-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK2-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK2-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK2-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK2-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK2: omp.inner.for.inc: |
| // CHECK2-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK2: omp.inner.for.end: |
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK2: omp.loop.exit: |
| // CHECK2-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK2-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK2: omp.precond.end: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK2-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK2-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK2-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK2-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK2-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK2-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK2-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK2-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK2-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK2-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK2-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK2-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK2-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK2-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK2-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK2: omp.precond.then: |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK2-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK2-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK2-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK2-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK2-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK2-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK2-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK2: cond.true: |
| // CHECK2-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK2-NEXT: br label [[COND_END:%.*]] |
| // CHECK2: cond.false: |
| // CHECK2-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: br label [[COND_END]] |
| // CHECK2: cond.end: |
| // CHECK2-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK2-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK2-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK2: omp.inner.for.cond: |
| // CHECK2-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK2-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK2-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK2: omp.inner.for.body: |
| // CHECK2-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK2-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK2-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK2-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK2-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 |
| // CHECK2-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK2-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK2-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK2-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK2-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 |
| // CHECK2-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK2: omp.body.continue: |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK2: omp.inner.for.inc: |
| // CHECK2-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK2-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK2-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK2: omp.inner.for.end: |
| // CHECK2-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK2: omp.loop.exit: |
| // CHECK2-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK2-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK2-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK2-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK2: omp.precond.end: |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK2-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK2-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK2-NEXT: entry: |
| // CHECK2-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK2-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@_Z16target_teams_funPi |
| // CHECK3-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[N:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 |
| // CHECK3-NEXT: [[TE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TH:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__CASTED3:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 8 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_5:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_6:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[N_CASTED9:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_BASEPTRS11:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_PTRS12:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK3-NEXT: [[DOTOFFLOAD_MAPPERS13:%.*]] = alloca [3 x i8*], align 8 |
| // CHECK3-NEXT: [[_TMP14:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_15:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_16:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: store i32 1000, i32* [[N]], align 4 |
| // CHECK3-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 |
| // CHECK3-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 |
| // CHECK3-NEXT: store i32 128, i32* [[TH]], align 4 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP3]], i32* [[CONV]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[CONV2:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP5]], i32* [[CONV2]], align 4 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED]], align 8 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__CASTED3]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP7]], i32* [[CONV4]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i64, i64* [[DOTCAPTURE_EXPR__CASTED3]], align 8 |
| // CHECK3-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP4]], i64* [[TMP10]], align 8 |
| // CHECK3-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP4]], i64* [[TMP12]], align 8 |
| // CHECK3-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP13]], align 8 |
| // CHECK3-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [1000 x i32]** |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP15]], align 8 |
| // CHECK3-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [1000 x i32]** |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP17]], align 8 |
| // CHECK3-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 1 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP18]], align 8 |
| // CHECK3-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP6]], i64* [[TMP20]], align 8 |
| // CHECK3-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP6]], i64* [[TMP22]], align 8 |
| // CHECK3-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 2 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP23]], align 8 |
| // CHECK3-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP8]], i64* [[TMP25]], align 8 |
| // CHECK3-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK3-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP8]], i64* [[TMP27]], align 8 |
| // CHECK3-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i64 0, i64 3 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP28]], align 8 |
| // CHECK3-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP30:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR_5]], align 4 |
| // CHECK3-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_5]], align 4 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP34]], 0 |
| // CHECK3-NEXT: [[DIV7:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[SUB8:%.*]] = sub nsw i32 [[DIV7]], 1 |
| // CHECK3-NEXT: store i32 [[SUB8]], i32* [[DOTCAPTURE_EXPR_6]], align 4 |
| // CHECK3-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_6]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP35]], 1 |
| // CHECK3-NEXT: [[TMP36:%.*]] = zext i32 [[ADD]] to i64 |
| // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP36]]) |
| // CHECK3-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.region_id, i32 4, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP31]], i32 [[TMP32]]) |
| // CHECK3-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 |
| // CHECK3-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK3: omp_offload.failed: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51(i64 [[TMP4]], [1000 x i32]* [[A]], i64 [[TMP6]], i64 [[TMP8]]) #[[ATTR2:[0-9]+]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK3: omp_offload.cont: |
| // CHECK3-NEXT: [[TMP39:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK3-NEXT: [[CONV10:%.*]] = bitcast i64* [[N_CASTED9]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP39]], i32* [[CONV10]], align 4 |
| // CHECK3-NEXT: [[TMP40:%.*]] = load i64, i64* [[N_CASTED9]], align 8 |
| // CHECK3-NEXT: [[TMP41:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP40]], i64* [[TMP43]], align 8 |
| // CHECK3-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i64* |
| // CHECK3-NEXT: store i64 [[TMP40]], i64* [[TMP45]], align 8 |
| // CHECK3-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 0 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP46]], align 8 |
| // CHECK3-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [1000 x i32]** |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP48]], align 8 |
| // CHECK3-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 1 |
| // CHECK3-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [1000 x i32]** |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP50]], align 8 |
| // CHECK3-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 1 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP51]], align 8 |
| // CHECK3-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32** |
| // CHECK3-NEXT: store i32* [[TMP41]], i32** [[TMP53]], align 8 |
| // CHECK3-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 2 |
| // CHECK3-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32** |
| // CHECK3-NEXT: store i32* [[TMP41]], i32** [[TMP55]], align 8 |
| // CHECK3-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS13]], i64 0, i64 2 |
| // CHECK3-NEXT: store i8* null, i8** [[TMP56]], align 8 |
| // CHECK3-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS11]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS12]], i32 0, i32 0 |
| // CHECK3-NEXT: [[TMP59:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_15]], align 4 |
| // CHECK3-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_15]], align 4 |
| // CHECK3-NEXT: [[SUB17:%.*]] = sub nsw i32 [[TMP60]], 0 |
| // CHECK3-NEXT: [[DIV18:%.*]] = sdiv i32 [[SUB17]], 1 |
| // CHECK3-NEXT: [[SUB19:%.*]] = sub nsw i32 [[DIV18]], 1 |
| // CHECK3-NEXT: store i32 [[SUB19]], i32* [[DOTCAPTURE_EXPR_16]], align 4 |
| // CHECK3-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_16]], align 4 |
| // CHECK3-NEXT: [[ADD20:%.*]] = add nsw i32 [[TMP61]], 1 |
| // CHECK3-NEXT: [[TMP62:%.*]] = zext i32 [[ADD20]] to i64 |
| // CHECK3-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP62]]) |
| // CHECK3-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.region_id, i32 3, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK3-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 |
| // CHECK3-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED21:%.*]], label [[OMP_OFFLOAD_CONT22:%.*]] |
| // CHECK3: omp_offload.failed21: |
| // CHECK3-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i64 [[TMP40]], [1000 x i32]* [[A]], i32* [[TMP41]]) #[[ATTR2]] |
| // CHECK3-NEXT: br label [[OMP_OFFLOAD_CONT22]] |
| // CHECK3: omp_offload.cont22: |
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i64 0, i64 0 |
| // CHECK3-NEXT: [[TMP65:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK3-NEXT: ret i32 [[TMP65]] |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK3-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) |
| // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK3-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* |
| // CHECK3-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 |
| // CHECK3-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK3: omp.precond.then: |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) |
| // CHECK3-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK3: omp.precond.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK3: omp.precond.then: |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK3-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 |
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK3-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK3-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK3-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK3-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK3: .cancel.exit: |
| // CHECK3-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK3: .cancel.continue: |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK3-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK3-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK3: cancel.exit: |
| // CHECK3-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK3-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK3: omp.precond.end: |
| // CHECK3-NEXT: br label [[CANCEL_CONT]] |
| // CHECK3: cancel.cont: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK3-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK3: omp.precond.then: |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK3-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK3-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK3-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK3-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK3-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK3: omp.precond.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK3-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK3-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK3-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK3-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK3-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK3-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK3-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK3-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK3-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK3-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK3-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK3-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK3-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK3-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK3-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK3: omp.precond.then: |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK3-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK3-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK3-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK3-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK3-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK3-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK3-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK3: cond.true: |
| // CHECK3-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK3-NEXT: br label [[COND_END:%.*]] |
| // CHECK3: cond.false: |
| // CHECK3-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: br label [[COND_END]] |
| // CHECK3: cond.end: |
| // CHECK3-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK3-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK3-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK3: omp.inner.for.cond: |
| // CHECK3-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK3-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK3-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK3: omp.inner.for.body: |
| // CHECK3-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK3-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK3-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK3-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK3-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 |
| // CHECK3-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK3-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK3-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK3-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK3-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 |
| // CHECK3-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK3: omp.body.continue: |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK3: omp.inner.for.inc: |
| // CHECK3-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK3-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK3-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK3: omp.inner.for.end: |
| // CHECK3-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK3: omp.loop.exit: |
| // CHECK3-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK3-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK3-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK3-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK3: omp.precond.end: |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK3-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK3-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK3-NEXT: entry: |
| // CHECK3-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK3-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@_Z16target_teams_funPi |
| // CHECK4-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[N:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 |
| // CHECK4-NEXT: [[TE:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TH:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_CASTED7:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK4-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK4-NEXT: [[_TMP11:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_13:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 1000, i32* [[N]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 |
| // CHECK4-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 |
| // CHECK4-NEXT: store i32 128, i32* [[TH]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 |
| // CHECK4-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 |
| // CHECK4-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 |
| // CHECK4-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP13]], align 4 |
| // CHECK4-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [1000 x i32]** |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP15]], align 4 |
| // CHECK4-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [1000 x i32]** |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP17]], align 4 |
| // CHECK4-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP18]], align 4 |
| // CHECK4-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4 |
| // CHECK4-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4 |
| // CHECK4-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP23]], align 4 |
| // CHECK4-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP25]], align 4 |
| // CHECK4-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK4-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP8]], i32* [[TMP27]], align 4 |
| // CHECK4-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP28]], align 4 |
| // CHECK4-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP30:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR_3]], align 4 |
| // CHECK4-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 |
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP34]], 0 |
| // CHECK4-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK4-NEXT: [[SUB6:%.*]] = sub nsw i32 [[DIV5]], 1 |
| // CHECK4-NEXT: store i32 [[SUB6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 |
| // CHECK4-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP35]], 1 |
| // CHECK4-NEXT: [[TMP36:%.*]] = zext i32 [[ADD]] to i64 |
| // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP36]]) |
| // CHECK4-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.region_id, i32 4, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP31]], i32 [[TMP32]]) |
| // CHECK4-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 |
| // CHECK4-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK4: omp_offload.failed: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51(i32 [[TMP4]], [1000 x i32]* [[A]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK4: omp_offload.cont: |
| // CHECK4-NEXT: [[TMP39:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP39]], i32* [[N_CASTED7]], align 4 |
| // CHECK4-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_CASTED7]], align 4 |
| // CHECK4-NEXT: [[TMP41:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP40]], i32* [[TMP43]], align 4 |
| // CHECK4-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* |
| // CHECK4-NEXT: store i32 [[TMP40]], i32* [[TMP45]], align 4 |
| // CHECK4-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP46]], align 4 |
| // CHECK4-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [1000 x i32]** |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP48]], align 4 |
| // CHECK4-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 |
| // CHECK4-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [1000 x i32]** |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP50]], align 4 |
| // CHECK4-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP51]], align 4 |
| // CHECK4-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32** |
| // CHECK4-NEXT: store i32* [[TMP41]], i32** [[TMP53]], align 4 |
| // CHECK4-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 2 |
| // CHECK4-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32** |
| // CHECK4-NEXT: store i32* [[TMP41]], i32** [[TMP55]], align 4 |
| // CHECK4-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 2 |
| // CHECK4-NEXT: store i8* null, i8** [[TMP56]], align 4 |
| // CHECK4-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP59:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_12]], align 4 |
| // CHECK4-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_12]], align 4 |
| // CHECK4-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP60]], 0 |
| // CHECK4-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 |
| // CHECK4-NEXT: [[SUB16:%.*]] = sub nsw i32 [[DIV15]], 1 |
| // CHECK4-NEXT: store i32 [[SUB16]], i32* [[DOTCAPTURE_EXPR_13]], align 4 |
| // CHECK4-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_13]], align 4 |
| // CHECK4-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP61]], 1 |
| // CHECK4-NEXT: [[TMP62:%.*]] = zext i32 [[ADD17]] to i64 |
| // CHECK4-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP62]]) |
| // CHECK4-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.region_id, i32 3, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK4-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 |
| // CHECK4-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] |
| // CHECK4: omp_offload.failed18: |
| // CHECK4-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i32 [[TMP40]], [1000 x i32]* [[A]], i32* [[TMP41]]) #[[ATTR2]] |
| // CHECK4-NEXT: br label [[OMP_OFFLOAD_CONT19]] |
| // CHECK4: omp_offload.cont19: |
| // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 |
| // CHECK4-NEXT: [[TMP65:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK4-NEXT: ret i32 [[TMP65]] |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK4: omp.precond.then: |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK4: cond.true: |
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: br label [[COND_END:%.*]] |
| // CHECK4: cond.false: |
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: br label [[COND_END]] |
| // CHECK4: cond.end: |
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK4: omp.inner.for.cond: |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK4: omp.inner.for.body: |
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK4: omp.inner.for.inc: |
| // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK4: omp.inner.for.end: |
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK4: omp.loop.exit: |
| // CHECK4-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) |
| // CHECK4-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK4: omp.precond.end: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK4: omp.precond.then: |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK4: cond.true: |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: br label [[COND_END:%.*]] |
| // CHECK4: cond.false: |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: br label [[COND_END]] |
| // CHECK4: cond.end: |
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK4: omp.inner.for.cond: |
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK4: omp.inner.for.body: |
| // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] |
| // CHECK4-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK4-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK4-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK4-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK4: .cancel.exit: |
| // CHECK4-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK4: .cancel.continue: |
| // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK4: omp.body.continue: |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK4: omp.inner.for.inc: |
| // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK4-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK4: omp.inner.for.end: |
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK4: omp.loop.exit: |
| // CHECK4-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK4-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK4: cancel.exit: |
| // CHECK4-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK4-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK4: omp.precond.end: |
| // CHECK4-NEXT: br label [[CANCEL_CONT]] |
| // CHECK4: cancel.cont: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK4-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK4: omp.precond.then: |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK4-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK4: cond.true: |
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: br label [[COND_END:%.*]] |
| // CHECK4: cond.false: |
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: br label [[COND_END]] |
| // CHECK4: cond.end: |
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK4: omp.inner.for.cond: |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK4: omp.inner.for.body: |
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK4-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK4: omp.inner.for.inc: |
| // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK4: omp.inner.for.end: |
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK4: omp.loop.exit: |
| // CHECK4-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK4-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK4: omp.precond.end: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK4-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK4-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK4-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK4-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK4-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK4-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK4-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK4-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK4-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK4: omp.precond.then: |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK4-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK4-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK4-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK4-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK4: cond.true: |
| // CHECK4-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK4-NEXT: br label [[COND_END:%.*]] |
| // CHECK4: cond.false: |
| // CHECK4-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: br label [[COND_END]] |
| // CHECK4: cond.end: |
| // CHECK4-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK4-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK4-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK4: omp.inner.for.cond: |
| // CHECK4-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK4-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK4-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK4: omp.inner.for.body: |
| // CHECK4-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK4-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK4-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK4-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK4-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 |
| // CHECK4-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK4-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK4-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] |
| // CHECK4-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 |
| // CHECK4-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK4: omp.body.continue: |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK4: omp.inner.for.inc: |
| // CHECK4-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK4-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK4-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK4: omp.inner.for.end: |
| // CHECK4-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK4: omp.loop.exit: |
| // CHECK4-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK4-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK4-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK4-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK4: omp.precond.end: |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK4-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK4-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK4-NEXT: entry: |
| // CHECK4-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK4-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@_Z16target_teams_funPi |
| // CHECK5-SAME: (i32* [[G:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[N:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A:%.*]] = alloca [1000 x i32], align 4 |
| // CHECK5-NEXT: [[TE:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[TH:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__CASTED2:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK5-NEXT: [[DOTOFFLOAD_PTRS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS:%.*]] = alloca [4 x i8*], align 4 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_3:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_4:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_CASTED7:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOFFLOAD_BASEPTRS8:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK5-NEXT: [[DOTOFFLOAD_PTRS9:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK5-NEXT: [[DOTOFFLOAD_MAPPERS10:%.*]] = alloca [3 x i8*], align 4 |
| // CHECK5-NEXT: [[_TMP11:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_12:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_13:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 1000, i32* [[N]], align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[TMP0]], 128 |
| // CHECK5-NEXT: store i32 [[DIV]], i32* [[TE]], align 4 |
| // CHECK5-NEXT: store i32 128, i32* [[TH]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[TE]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[TH]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP3]], i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP7]], i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__CASTED2]], align 4 |
| // CHECK5-NEXT: [[TMP9:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP10:%.*]] = bitcast i8** [[TMP9]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[TMP10]], align 4 |
| // CHECK5-NEXT: [[TMP11:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP12:%.*]] = bitcast i8** [[TMP11]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[TMP12]], align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 0 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP13]], align 4 |
| // CHECK5-NEXT: [[TMP14:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 1 |
| // CHECK5-NEXT: [[TMP15:%.*]] = bitcast i8** [[TMP14]] to [1000 x i32]** |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP15]], align 4 |
| // CHECK5-NEXT: [[TMP16:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 1 |
| // CHECK5-NEXT: [[TMP17:%.*]] = bitcast i8** [[TMP16]] to [1000 x i32]** |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP17]], align 4 |
| // CHECK5-NEXT: [[TMP18:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 1 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP18]], align 4 |
| // CHECK5-NEXT: [[TMP19:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 2 |
| // CHECK5-NEXT: [[TMP20:%.*]] = bitcast i8** [[TMP19]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP6]], i32* [[TMP20]], align 4 |
| // CHECK5-NEXT: [[TMP21:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 2 |
| // CHECK5-NEXT: [[TMP22:%.*]] = bitcast i8** [[TMP21]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP6]], i32* [[TMP22]], align 4 |
| // CHECK5-NEXT: [[TMP23:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 2 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP23]], align 4 |
| // CHECK5-NEXT: [[TMP24:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 3 |
| // CHECK5-NEXT: [[TMP25:%.*]] = bitcast i8** [[TMP24]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP8]], i32* [[TMP25]], align 4 |
| // CHECK5-NEXT: [[TMP26:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 3 |
| // CHECK5-NEXT: [[TMP27:%.*]] = bitcast i8** [[TMP26]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP8]], i32* [[TMP27]], align 4 |
| // CHECK5-NEXT: [[TMP28:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_MAPPERS]], i32 0, i32 3 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP28]], align 4 |
| // CHECK5-NEXT: [[TMP29:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_BASEPTRS]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP30:%.*]] = getelementptr inbounds [4 x i8*], [4 x i8*]* [[DOTOFFLOAD_PTRS]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP31:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[TMP32:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: [[TMP33:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP33]], i32* [[DOTCAPTURE_EXPR_3]], align 4 |
| // CHECK5-NEXT: [[TMP34:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_3]], align 4 |
| // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP34]], 0 |
| // CHECK5-NEXT: [[DIV5:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK5-NEXT: [[SUB6:%.*]] = sub nsw i32 [[DIV5]], 1 |
| // CHECK5-NEXT: store i32 [[SUB6]], i32* [[DOTCAPTURE_EXPR_4]], align 4 |
| // CHECK5-NEXT: [[TMP35:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_4]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP35]], 1 |
| // CHECK5-NEXT: [[TMP36:%.*]] = zext i32 [[ADD]] to i64 |
| // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3:[0-9]+]], i64 -1, i64 [[TMP36]]) |
| // CHECK5-NEXT: [[TMP37:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51.region_id, i32 4, i8** [[TMP29]], i8** [[TMP30]], i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_sizes, i32 0, i32 0), i64* getelementptr inbounds ([4 x i64], [4 x i64]* @.offload_maptypes, i32 0, i32 0), i8** null, i8** null, i32 [[TMP31]], i32 [[TMP32]]) |
| // CHECK5-NEXT: [[TMP38:%.*]] = icmp ne i32 [[TMP37]], 0 |
| // CHECK5-NEXT: br i1 [[TMP38]], label [[OMP_OFFLOAD_FAILED:%.*]], label [[OMP_OFFLOAD_CONT:%.*]] |
| // CHECK5: omp_offload.failed: |
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51(i32 [[TMP4]], [1000 x i32]* [[A]], i32 [[TMP6]], i32 [[TMP8]]) #[[ATTR2:[0-9]+]] |
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT]] |
| // CHECK5: omp_offload.cont: |
| // CHECK5-NEXT: [[TMP39:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP39]], i32* [[N_CASTED7]], align 4 |
| // CHECK5-NEXT: [[TMP40:%.*]] = load i32, i32* [[N_CASTED7]], align 4 |
| // CHECK5-NEXT: [[TMP41:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP42:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP43:%.*]] = bitcast i8** [[TMP42]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP40]], i32* [[TMP43]], align 4 |
| // CHECK5-NEXT: [[TMP44:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP45:%.*]] = bitcast i8** [[TMP44]] to i32* |
| // CHECK5-NEXT: store i32 [[TMP40]], i32* [[TMP45]], align 4 |
| // CHECK5-NEXT: [[TMP46:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 0 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP46]], align 4 |
| // CHECK5-NEXT: [[TMP47:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 1 |
| // CHECK5-NEXT: [[TMP48:%.*]] = bitcast i8** [[TMP47]] to [1000 x i32]** |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP48]], align 4 |
| // CHECK5-NEXT: [[TMP49:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 1 |
| // CHECK5-NEXT: [[TMP50:%.*]] = bitcast i8** [[TMP49]] to [1000 x i32]** |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[TMP50]], align 4 |
| // CHECK5-NEXT: [[TMP51:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 1 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP51]], align 4 |
| // CHECK5-NEXT: [[TMP52:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 2 |
| // CHECK5-NEXT: [[TMP53:%.*]] = bitcast i8** [[TMP52]] to i32** |
| // CHECK5-NEXT: store i32* [[TMP41]], i32** [[TMP53]], align 4 |
| // CHECK5-NEXT: [[TMP54:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 2 |
| // CHECK5-NEXT: [[TMP55:%.*]] = bitcast i8** [[TMP54]] to i32** |
| // CHECK5-NEXT: store i32* [[TMP41]], i32** [[TMP55]], align 4 |
| // CHECK5-NEXT: [[TMP56:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_MAPPERS10]], i32 0, i32 2 |
| // CHECK5-NEXT: store i8* null, i8** [[TMP56]], align 4 |
| // CHECK5-NEXT: [[TMP57:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_BASEPTRS8]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP58:%.*]] = getelementptr inbounds [3 x i8*], [3 x i8*]* [[DOTOFFLOAD_PTRS9]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP59:%.*]] = load i32, i32* [[N]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP59]], i32* [[DOTCAPTURE_EXPR_12]], align 4 |
| // CHECK5-NEXT: [[TMP60:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_12]], align 4 |
| // CHECK5-NEXT: [[SUB14:%.*]] = sub nsw i32 [[TMP60]], 0 |
| // CHECK5-NEXT: [[DIV15:%.*]] = sdiv i32 [[SUB14]], 1 |
| // CHECK5-NEXT: [[SUB16:%.*]] = sub nsw i32 [[DIV15]], 1 |
| // CHECK5-NEXT: store i32 [[SUB16]], i32* [[DOTCAPTURE_EXPR_13]], align 4 |
| // CHECK5-NEXT: [[TMP61:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_13]], align 4 |
| // CHECK5-NEXT: [[ADD17:%.*]] = add nsw i32 [[TMP61]], 1 |
| // CHECK5-NEXT: [[TMP62:%.*]] = zext i32 [[ADD17]] to i64 |
| // CHECK5-NEXT: call void @__kmpc_push_target_tripcount_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i64 [[TMP62]]) |
| // CHECK5-NEXT: [[TMP63:%.*]] = call i32 @__tgt_target_teams_mapper(%struct.ident_t* @[[GLOB3]], i64 -1, i8* @.{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58.region_id, i32 3, i8** [[TMP57]], i8** [[TMP58]], i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_sizes.4, i32 0, i32 0), i64* getelementptr inbounds ([3 x i64], [3 x i64]* @.offload_maptypes.5, i32 0, i32 0), i8** null, i8** null, i32 0, i32 0) |
| // CHECK5-NEXT: [[TMP64:%.*]] = icmp ne i32 [[TMP63]], 0 |
| // CHECK5-NEXT: br i1 [[TMP64]], label [[OMP_OFFLOAD_FAILED18:%.*]], label [[OMP_OFFLOAD_CONT19:%.*]] |
| // CHECK5: omp_offload.failed18: |
| // CHECK5-NEXT: call void @{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58(i32 [[TMP40]], [1000 x i32]* [[A]], i32* [[TMP41]]) #[[ATTR2]] |
| // CHECK5-NEXT: br label [[OMP_OFFLOAD_CONT19]] |
| // CHECK5: omp_offload.cont19: |
| // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[A]], i32 0, i32 0 |
| // CHECK5-NEXT: [[TMP65:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK5-NEXT: ret i32 [[TMP65]] |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK5-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR1:[0-9]+]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3]]) |
| // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK5: omp.precond.then: |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK5: cond.true: |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: br label [[COND_END:%.*]] |
| // CHECK5: cond.false: |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: br label [[COND_END]] |
| // CHECK5: cond.end: |
| // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK5: omp.inner.for.cond: |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK5: omp.inner.for.body: |
| // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK5: omp.inner.for.inc: |
| // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] |
| // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK5: omp.inner.for.end: |
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK5: omp.loop.exit: |
| // CHECK5-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) |
| // CHECK5-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK5: omp.precond.end: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR1]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK5: omp.precond.then: |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK5: cond.true: |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: br label [[COND_END:%.*]] |
| // CHECK5: cond.false: |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: br label [[COND_END]] |
| // CHECK5: cond.end: |
| // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK5: omp.inner.for.cond: |
| // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK5: omp.inner.for.body: |
| // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] |
| // CHECK5-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK5-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK5-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK5-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK5-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK5: .cancel.exit: |
| // CHECK5-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK5: .cancel.continue: |
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK5: omp.body.continue: |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK5: omp.inner.for.inc: |
| // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK5-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK5: omp.inner.for.end: |
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK5: omp.loop.exit: |
| // CHECK5-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK5-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK5: cancel.exit: |
| // CHECK5-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK5-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK5: omp.precond.end: |
| // CHECK5-NEXT: br label [[CANCEL_CONT]] |
| // CHECK5: cancel.cont: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK5-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK5: omp.precond.then: |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK5: cond.true: |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: br label [[COND_END:%.*]] |
| // CHECK5: cond.false: |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: br label [[COND_END]] |
| // CHECK5: cond.end: |
| // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK5: omp.inner.for.cond: |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK5: omp.inner.for.body: |
| // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK5-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK5: omp.inner.for.inc: |
| // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] |
| // CHECK5-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK5: omp.inner.for.end: |
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK5: omp.loop.exit: |
| // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK5-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK5: omp.precond.end: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK5-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR1]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK5-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK5-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK5-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK5-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK5-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK5-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK5-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK5-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK5: omp.precond.then: |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK5-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK5-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK5-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK5-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK5-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK5: cond.true: |
| // CHECK5-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK5-NEXT: br label [[COND_END:%.*]] |
| // CHECK5: cond.false: |
| // CHECK5-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: br label [[COND_END]] |
| // CHECK5: cond.end: |
| // CHECK5-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK5-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK5-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK5: omp.inner.for.cond: |
| // CHECK5-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK5-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK5-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK5: omp.inner.for.body: |
| // CHECK5-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK5-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK5-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK5-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK5-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 |
| // CHECK5-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK5-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK5-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] |
| // CHECK5-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 |
| // CHECK5-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK5: omp.body.continue: |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK5: omp.inner.for.inc: |
| // CHECK5-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK5-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK5-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK5: omp.inner.for.end: |
| // CHECK5-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK5: omp.loop.exit: |
| // CHECK5-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK5-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK5-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK5-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK5: omp.precond.end: |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK5-LABEL: define {{[^@]+}}@.omp_offloading.requires_reg |
| // CHECK5-SAME: () #[[ATTR3:[0-9]+]] { |
| // CHECK5-NEXT: entry: |
| // CHECK5-NEXT: call void @__tgt_register_requires(i64 1) |
| // CHECK5-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) |
| // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* |
| // CHECK10-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 |
| // CHECK10-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK10: omp.precond.then: |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK10: cond.true: |
| // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: br label [[COND_END:%.*]] |
| // CHECK10: cond.false: |
| // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: br label [[COND_END]] |
| // CHECK10: cond.end: |
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK10: omp.inner.for.cond: |
| // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK10: omp.inner.for.body: |
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK10: omp.inner.for.inc: |
| // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK10: omp.inner.for.end: |
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK10: omp.loop.exit: |
| // CHECK10-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) |
| // CHECK10-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK10: omp.precond.end: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK10: omp.precond.then: |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK10: cond.true: |
| // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: br label [[COND_END:%.*]] |
| // CHECK10: cond.false: |
| // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: br label [[COND_END]] |
| // CHECK10: cond.end: |
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK10: omp.inner.for.cond: |
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK10: omp.inner.for.body: |
| // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK10-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 |
| // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK10-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK10-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK10-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK10-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK10-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK10: .cancel.exit: |
| // CHECK10-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK10: .cancel.continue: |
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK10: omp.body.continue: |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK10: omp.inner.for.inc: |
| // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK10-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK10: omp.inner.for.end: |
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK10: omp.loop.exit: |
| // CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK10-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK10: cancel.exit: |
| // CHECK10-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK10-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK10: omp.precond.end: |
| // CHECK10-NEXT: br label [[CANCEL_CONT]] |
| // CHECK10: cancel.cont: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK10-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK10: omp.precond.then: |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK10-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK10-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK10: cond.true: |
| // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: br label [[COND_END:%.*]] |
| // CHECK10: cond.false: |
| // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: br label [[COND_END]] |
| // CHECK10: cond.end: |
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK10: omp.inner.for.cond: |
| // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK10-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK10: omp.inner.for.body: |
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK10-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK10-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK10-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK10-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK10-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK10-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK10: omp.inner.for.inc: |
| // CHECK10-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK10: omp.inner.for.end: |
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK10: omp.loop.exit: |
| // CHECK10-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK10-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK10: omp.precond.end: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK10-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK10-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK10-NEXT: entry: |
| // CHECK10-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK10-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK10-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK10-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK10-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK10-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK10-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK10-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK10-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK10-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK10-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK10-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK10-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK10-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK10-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK10: omp.precond.then: |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK10-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK10-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK10-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK10-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK10-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK10-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK10-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK10: cond.true: |
| // CHECK10-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK10-NEXT: br label [[COND_END:%.*]] |
| // CHECK10: cond.false: |
| // CHECK10-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: br label [[COND_END]] |
| // CHECK10: cond.end: |
| // CHECK10-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK10-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK10-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK10: omp.inner.for.cond: |
| // CHECK10-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK10-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK10-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK10: omp.inner.for.body: |
| // CHECK10-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK10-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK10-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK10-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK10-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 |
| // CHECK10-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK10-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK10-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK10-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK10-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 |
| // CHECK10-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK10: omp.body.continue: |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK10: omp.inner.for.inc: |
| // CHECK10-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK10-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK10-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK10: omp.inner.for.end: |
| // CHECK10-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK10: omp.loop.exit: |
| // CHECK10-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK10-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK10-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK10-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK10: omp.precond.end: |
| // CHECK10-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i64 [[DOTCAPTURE_EXPR_:%.*]], i64 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) |
| // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_]], i64* [[DOTCAPTURE_EXPR__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[DOTCAPTURE_EXPR_1]], i64* [[DOTCAPTURE_EXPR__ADDR2]], align 8 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK11-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV3:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR]] to i32* |
| // CHECK11-NEXT: [[CONV4:%.*]] = bitcast i64* [[DOTCAPTURE_EXPR__ADDR2]] to i32* |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[CONV3]], align 8 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[CONV4]], align 8 |
| // CHECK11-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: [[CONV5:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP4]], i32* [[CONV5]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i64 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK11: omp.precond.then: |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]]) |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP20]], [[TMP21]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP23:%.*]] = load i32, i32* [[TMP22]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP23]]) |
| // CHECK11-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK11: omp.precond.end: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK11: omp.precond.then: |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK11-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK11-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP17]] to i64 |
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK11-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK11-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK11-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK11-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK11: .cancel.exit: |
| // CHECK11-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK11: .cancel.continue: |
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK11: omp.body.continue: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[ADD8:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK11-NEXT: store i32 [[ADD8]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK11-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK11: cancel.exit: |
| // CHECK11-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK11-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK11: omp.precond.end: |
| // CHECK11-NEXT: br label [[CANCEL_CONT]] |
| // CHECK11: cancel.cont: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK11-SAME: (i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: [[CONV1:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP1]], i32* [[CONV1]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i64 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[N_CASTED:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK11: omp.precond.then: |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK11-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK11-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = zext i32 [[TMP14]] to i64 |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = zext i32 [[TMP16]] to i64 |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: [[CONV6:%.*]] = bitcast i64* [[N_CASTED]] to i32* |
| // CHECK11-NEXT: store i32 [[TMP18]], i32* [[CONV6]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i64, i64* [[N_CASTED]], align 8 |
| // CHECK11-NEXT: [[TMP20:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK11-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i64, i64, i64, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i64 [[TMP15]], i64 [[TMP17]], i64 [[TMP19]], [1000 x i32]* [[TMP0]], i32* [[TMP20]]) |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP21]], [[TMP22]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK11-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK11: omp.precond.end: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK11-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK11-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i64 [[DOTPREVIOUS_LB_:%.*]], i64 [[DOTPREVIOUS_UB_:%.*]], i64 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK11-NEXT: entry: |
| // CHECK11-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[N_ADDR:%.*]] = alloca i64, align 8 |
| // CHECK11-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 8 |
| // CHECK11-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 8 |
| // CHECK11-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: [[I5:%.*]] = alloca i32, align 4 |
| // CHECK11-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[DOTPREVIOUS_LB_]], i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[DOTPREVIOUS_UB_]], i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK11-NEXT: store i64 [[N]], i64* [[N_ADDR]], align 8 |
| // CHECK11-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV:%.*]] = bitcast i64* [[N_ADDR]] to i32* |
| // CHECK11-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP1:%.*]] = load i32, i32* [[CONV]], align 8 |
| // CHECK11-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK11-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK11-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK11-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK11-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK11-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK11-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK11: omp.precond.then: |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP5:%.*]] = load i64, i64* [[DOTPREVIOUS_LB__ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV3:%.*]] = trunc i64 [[TMP5]] to i32 |
| // CHECK11-NEXT: [[TMP6:%.*]] = load i64, i64* [[DOTPREVIOUS_UB__ADDR]], align 8 |
| // CHECK11-NEXT: [[CONV4:%.*]] = trunc i64 [[TMP6]] to i32 |
| // CHECK11-NEXT: store i32 [[CONV3]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[CONV4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK11-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK11-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK11-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: [[CMP6:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK11-NEXT: br i1 [[CMP6]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK11: cond.true: |
| // CHECK11-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK11-NEXT: br label [[COND_END:%.*]] |
| // CHECK11: cond.false: |
| // CHECK11-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: br label [[COND_END]] |
| // CHECK11: cond.end: |
| // CHECK11-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK11-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK11-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK11: omp.inner.for.cond: |
| // CHECK11-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK11-NEXT: [[CMP7:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK11-NEXT: br i1 [[CMP7]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK11: omp.inner.for.body: |
| // CHECK11-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK11-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK11-NEXT: store i32 [[ADD]], i32* [[I5]], align 4 |
| // CHECK11-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 8 |
| // CHECK11-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i64 0 |
| // CHECK11-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK11-NEXT: [[TMP19:%.*]] = load i32, i32* [[I5]], align 4 |
| // CHECK11-NEXT: [[IDXPROM:%.*]] = sext i32 [[TMP19]] to i64 |
| // CHECK11-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i64 0, i64 [[IDXPROM]] |
| // CHECK11-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX8]], align 4 |
| // CHECK11-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK11: omp.body.continue: |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK11: omp.inner.for.inc: |
| // CHECK11-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: [[ADD9:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK11-NEXT: store i32 [[ADD9]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK11-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK11: omp.inner.for.end: |
| // CHECK11-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK11: omp.loop.exit: |
| // CHECK11-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 8 |
| // CHECK11-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK11-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK11-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK11: omp.precond.end: |
| // CHECK11-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) |
| // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK12: omp.precond.then: |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK12: cond.true: |
| // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: br label [[COND_END:%.*]] |
| // CHECK12: cond.false: |
| // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: br label [[COND_END]] |
| // CHECK12: cond.end: |
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK12: omp.inner.for.cond: |
| // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK12: omp.inner.for.body: |
| // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK12: omp.inner.for.inc: |
| // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK12: omp.inner.for.end: |
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK12: omp.loop.exit: |
| // CHECK12-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) |
| // CHECK12-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK12: omp.precond.end: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK12: omp.precond.then: |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK12: cond.true: |
| // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: br label [[COND_END:%.*]] |
| // CHECK12: cond.false: |
| // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: br label [[COND_END]] |
| // CHECK12: cond.end: |
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK12: omp.inner.for.cond: |
| // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK12: omp.inner.for.body: |
| // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] |
| // CHECK12-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK12-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK12-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK12-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK12: .cancel.exit: |
| // CHECK12-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK12: .cancel.continue: |
| // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK12: omp.body.continue: |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK12: omp.inner.for.inc: |
| // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK12-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK12: omp.inner.for.end: |
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK12: omp.loop.exit: |
| // CHECK12-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK12-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK12: cancel.exit: |
| // CHECK12-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK12-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK12: omp.precond.end: |
| // CHECK12-NEXT: br label [[CANCEL_CONT]] |
| // CHECK12: cancel.cont: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK12-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK12: omp.precond.then: |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK12-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK12: cond.true: |
| // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: br label [[COND_END:%.*]] |
| // CHECK12: cond.false: |
| // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: br label [[COND_END]] |
| // CHECK12: cond.end: |
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK12: omp.inner.for.cond: |
| // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK12: omp.inner.for.body: |
| // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK12-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK12-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK12: omp.inner.for.inc: |
| // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK12: omp.inner.for.end: |
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK12: omp.loop.exit: |
| // CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK12-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK12: omp.precond.end: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK12-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK12-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK12-NEXT: entry: |
| // CHECK12-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK12-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK12-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK12-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK12-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK12-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK12-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK12-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK12-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK12: omp.precond.then: |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK12-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK12-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK12-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK12-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK12: cond.true: |
| // CHECK12-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK12-NEXT: br label [[COND_END:%.*]] |
| // CHECK12: cond.false: |
| // CHECK12-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: br label [[COND_END]] |
| // CHECK12: cond.end: |
| // CHECK12-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK12-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK12-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK12: omp.inner.for.cond: |
| // CHECK12-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK12-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK12-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK12: omp.inner.for.body: |
| // CHECK12-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK12-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK12-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK12-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 |
| // CHECK12-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK12-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK12-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] |
| // CHECK12-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 |
| // CHECK12-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK12: omp.body.continue: |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK12: omp.inner.for.inc: |
| // CHECK12-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK12-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK12-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK12: omp.inner.for.end: |
| // CHECK12-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK12: omp.loop.exit: |
| // CHECK12-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK12-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK12-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK12-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK12: omp.precond.end: |
| // CHECK12-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l51 |
| // CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32 [[DOTCAPTURE_EXPR_:%.*]], i32 [[DOTCAPTURE_EXPR_1:%.*]]) #[[ATTR0:[0-9]+]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR__ADDR2:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(%struct.ident_t* @[[GLOB3:[0-9]+]]) |
| // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[DOTCAPTURE_EXPR_]], i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[DOTCAPTURE_EXPR_1]], i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR__ADDR2]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_push_num_teams(%struct.ident_t* @[[GLOB3]], i32 [[TMP0]], i32 [[TMP2]], i32 [[TMP3]]) |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 2, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*)* @.omp_outlined. to void (i32*, i32*, ...)*), i32 [[TMP5]], [1000 x i32]* [[TMP1]]) |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined. |
| // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK13: omp.precond.then: |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1:[0-9]+]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK13: cond.true: |
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: br label [[COND_END:%.*]] |
| // CHECK13: cond.false: |
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: br label [[COND_END]] |
| // CHECK13: cond.end: |
| // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK13: omp.inner.for.cond: |
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK13: omp.inner.for.body: |
| // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 4, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*)* @.omp_outlined..1 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]]) |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK13: omp.inner.for.inc: |
| // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP18]], [[TMP19]] |
| // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK13: omp.inner.for.end: |
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK13: omp.loop.exit: |
| // CHECK13-NEXT: [[TMP20:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP21:%.*]] = load i32, i32* [[TMP20]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP21]]) |
| // CHECK13-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK13: omp.precond.end: |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..1 |
| // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]]) #[[ATTR0]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK13: omp.precond.then: |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2:[0-9]+]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK13: cond.true: |
| // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: br label [[COND_END:%.*]] |
| // CHECK13: cond.false: |
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: br label [[COND_END]] |
| // CHECK13: cond.end: |
| // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK13: omp.inner.for.cond: |
| // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK13: omp.inner.for.body: |
| // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP17]] |
| // CHECK13-NEXT: store i32 0, i32* [[ARRAYIDX]], align 4 |
| // CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[TMP18]], align 4 |
| // CHECK13-NEXT: [[TMP20:%.*]] = call i32 @__kmpc_cancel(%struct.ident_t* @[[GLOB3]], i32 [[TMP19]], i32 2) |
| // CHECK13-NEXT: [[TMP21:%.*]] = icmp ne i32 [[TMP20]], 0 |
| // CHECK13-NEXT: br i1 [[TMP21]], label [[DOTCANCEL_EXIT:%.*]], label [[DOTCANCEL_CONTINUE:%.*]] |
| // CHECK13: .cancel.exit: |
| // CHECK13-NEXT: br label [[CANCEL_EXIT:%.*]] |
| // CHECK13: .cancel.continue: |
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK13: omp.body.continue: |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK13: omp.inner.for.inc: |
| // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[ADD6:%.*]] = add nsw i32 [[TMP22]], 1 |
| // CHECK13-NEXT: store i32 [[ADD6]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK13: omp.inner.for.end: |
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK13: omp.loop.exit: |
| // CHECK13-NEXT: [[TMP23:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP24:%.*]] = load i32, i32* [[TMP23]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP24]]) |
| // CHECK13-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK13: cancel.exit: |
| // CHECK13-NEXT: [[TMP25:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP26:%.*]] = load i32, i32* [[TMP25]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP26]]) |
| // CHECK13-NEXT: br label [[CANCEL_CONT:%.*]] |
| // CHECK13: omp.precond.end: |
| // CHECK13-NEXT: br label [[CANCEL_CONT]] |
| // CHECK13: cancel.cont: |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@{{__omp_offloading_[0-9a-z]+_[0-9a-z]+}}__Z16target_teams_funPi_l58 |
| // CHECK13-SAME: (i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP1]], i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_teams(%struct.ident_t* @[[GLOB3]], i32 3, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, [1000 x i32]*, i32*)* @.omp_outlined..2 to void (i32*, i32*, ...)*), i32 [[TMP2]], [1000 x i32]* [[TMP0]], i32* [[TMP3]]) |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..2 |
| // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_COMB_LB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_COMB_UB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[N_CASTED:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK13: omp.precond.then: |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK13-NEXT: [[TMP5:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[TMP5]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB1]], i32 [[TMP6]], i32 92, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_COMB_LB]], i32* [[DOTOMP_COMB_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK13-NEXT: [[TMP7:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP7]], [[TMP8]] |
| // CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK13: cond.true: |
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: br label [[COND_END:%.*]] |
| // CHECK13: cond.false: |
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: br label [[COND_END]] |
| // CHECK13: cond.end: |
| // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP9]], [[COND_TRUE]] ], [ [[TMP10]], [[COND_FALSE]] ] |
| // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP11]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK13: omp.inner.for.cond: |
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP12]], [[TMP13]] |
| // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK13: omp.inner.for.body: |
| // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_COMB_LB]], align 4 |
| // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_COMB_UB]], align 4 |
| // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP16]], i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: [[TMP17:%.*]] = load i32, i32* [[N_CASTED]], align 4 |
| // CHECK13-NEXT: [[TMP18:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK13-NEXT: call void (%struct.ident_t*, i32, void (i32*, i32*, ...)*, ...) @__kmpc_fork_call(%struct.ident_t* @[[GLOB3]], i32 5, void (i32*, i32*, ...)* bitcast (void (i32*, i32*, i32, i32, i32, [1000 x i32]*, i32*)* @.omp_outlined..3 to void (i32*, i32*, ...)*), i32 [[TMP14]], i32 [[TMP15]], i32 [[TMP17]], [1000 x i32]* [[TMP0]], i32* [[TMP18]]) |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK13: omp.inner.for.inc: |
| // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 [[TMP19]], [[TMP20]] |
| // CHECK13-NEXT: store i32 [[ADD]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK13: omp.inner.for.end: |
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK13: omp.loop.exit: |
| // CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK13-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK13: omp.precond.end: |
| // CHECK13-NEXT: ret void |
| // |
| // |
| // CHECK13-LABEL: define {{[^@]+}}@.omp_outlined..3 |
| // CHECK13-SAME: (i32* noalias [[DOTGLOBAL_TID_:%.*]], i32* noalias [[DOTBOUND_TID_:%.*]], i32 [[DOTPREVIOUS_LB_:%.*]], i32 [[DOTPREVIOUS_UB_:%.*]], i32 [[N:%.*]], [1000 x i32]* nonnull align 4 dereferenceable(4000) [[A:%.*]], i32* [[G:%.*]]) #[[ATTR0]] { |
| // CHECK13-NEXT: entry: |
| // CHECK13-NEXT: [[DOTGLOBAL_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTBOUND_TID__ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTPREVIOUS_LB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTPREVIOUS_UB__ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[N_ADDR:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[A_ADDR:%.*]] = alloca [1000 x i32]*, align 4 |
| // CHECK13-NEXT: [[G_ADDR:%.*]] = alloca i32*, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IV:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[TMP:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTCAPTURE_EXPR_1:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_LB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_UB:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_STRIDE:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[DOTOMP_IS_LAST:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: [[I3:%.*]] = alloca i32, align 4 |
| // CHECK13-NEXT: store i32* [[DOTGLOBAL_TID_]], i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[DOTBOUND_TID_]], i32** [[DOTBOUND_TID__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[DOTPREVIOUS_LB_]], i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[DOTPREVIOUS_UB_]], i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[N]], i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store [1000 x i32]* [[A]], [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: store i32* [[G]], i32** [[G_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP0:%.*]] = load [1000 x i32]*, [1000 x i32]** [[A_ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP1:%.*]] = load i32, i32* [[N_ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP1]], i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[TMP2:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[SUB:%.*]] = sub nsw i32 [[TMP2]], 0 |
| // CHECK13-NEXT: [[DIV:%.*]] = sdiv i32 [[SUB]], 1 |
| // CHECK13-NEXT: [[SUB2:%.*]] = sub nsw i32 [[DIV]], 1 |
| // CHECK13-NEXT: store i32 [[SUB2]], i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[I]], align 4 |
| // CHECK13-NEXT: [[TMP3:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_]], align 4 |
| // CHECK13-NEXT: [[CMP:%.*]] = icmp slt i32 0, [[TMP3]] |
| // CHECK13-NEXT: br i1 [[CMP]], label [[OMP_PRECOND_THEN:%.*]], label [[OMP_PRECOND_END:%.*]] |
| // CHECK13: omp.precond.then: |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: [[TMP4:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP4]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP5:%.*]] = load i32, i32* [[DOTPREVIOUS_LB__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP6:%.*]] = load i32, i32* [[DOTPREVIOUS_UB__ADDR]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP5]], i32* [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP6]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: store i32 1, i32* [[DOTOMP_STRIDE]], align 4 |
| // CHECK13-NEXT: store i32 0, i32* [[DOTOMP_IS_LAST]], align 4 |
| // CHECK13-NEXT: [[TMP7:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP8:%.*]] = load i32, i32* [[TMP7]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_init_4(%struct.ident_t* @[[GLOB2]], i32 [[TMP8]], i32 34, i32* [[DOTOMP_IS_LAST]], i32* [[DOTOMP_LB]], i32* [[DOTOMP_UB]], i32* [[DOTOMP_STRIDE]], i32 1, i32 1) |
| // CHECK13-NEXT: [[TMP9:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP10:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: [[CMP4:%.*]] = icmp sgt i32 [[TMP9]], [[TMP10]] |
| // CHECK13-NEXT: br i1 [[CMP4]], label [[COND_TRUE:%.*]], label [[COND_FALSE:%.*]] |
| // CHECK13: cond.true: |
| // CHECK13-NEXT: [[TMP11:%.*]] = load i32, i32* [[DOTCAPTURE_EXPR_1]], align 4 |
| // CHECK13-NEXT: br label [[COND_END:%.*]] |
| // CHECK13: cond.false: |
| // CHECK13-NEXT: [[TMP12:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: br label [[COND_END]] |
| // CHECK13: cond.end: |
| // CHECK13-NEXT: [[COND:%.*]] = phi i32 [ [[TMP11]], [[COND_TRUE]] ], [ [[TMP12]], [[COND_FALSE]] ] |
| // CHECK13-NEXT: store i32 [[COND]], i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[TMP13:%.*]] = load i32, i32* [[DOTOMP_LB]], align 4 |
| // CHECK13-NEXT: store i32 [[TMP13]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND:%.*]] |
| // CHECK13: omp.inner.for.cond: |
| // CHECK13-NEXT: [[TMP14:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[TMP15:%.*]] = load i32, i32* [[DOTOMP_UB]], align 4 |
| // CHECK13-NEXT: [[CMP5:%.*]] = icmp sle i32 [[TMP14]], [[TMP15]] |
| // CHECK13-NEXT: br i1 [[CMP5]], label [[OMP_INNER_FOR_BODY:%.*]], label [[OMP_INNER_FOR_END:%.*]] |
| // CHECK13: omp.inner.for.body: |
| // CHECK13-NEXT: [[TMP16:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[MUL:%.*]] = mul nsw i32 [[TMP16]], 1 |
| // CHECK13-NEXT: [[ADD:%.*]] = add nsw i32 0, [[MUL]] |
| // CHECK13-NEXT: store i32 [[ADD]], i32* [[I3]], align 4 |
| // CHECK13-NEXT: [[TMP17:%.*]] = load i32*, i32** [[G_ADDR]], align 4 |
| // CHECK13-NEXT: [[ARRAYIDX:%.*]] = getelementptr inbounds i32, i32* [[TMP17]], i32 0 |
| // CHECK13-NEXT: [[TMP18:%.*]] = load i32, i32* [[ARRAYIDX]], align 4 |
| // CHECK13-NEXT: [[TMP19:%.*]] = load i32, i32* [[I3]], align 4 |
| // CHECK13-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds [1000 x i32], [1000 x i32]* [[TMP0]], i32 0, i32 [[TMP19]] |
| // CHECK13-NEXT: store i32 [[TMP18]], i32* [[ARRAYIDX6]], align 4 |
| // CHECK13-NEXT: br label [[OMP_BODY_CONTINUE:%.*]] |
| // CHECK13: omp.body.continue: |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_INC:%.*]] |
| // CHECK13: omp.inner.for.inc: |
| // CHECK13-NEXT: [[TMP20:%.*]] = load i32, i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: [[ADD7:%.*]] = add nsw i32 [[TMP20]], 1 |
| // CHECK13-NEXT: store i32 [[ADD7]], i32* [[DOTOMP_IV]], align 4 |
| // CHECK13-NEXT: br label [[OMP_INNER_FOR_COND]] |
| // CHECK13: omp.inner.for.end: |
| // CHECK13-NEXT: br label [[OMP_LOOP_EXIT:%.*]] |
| // CHECK13: omp.loop.exit: |
| // CHECK13-NEXT: [[TMP21:%.*]] = load i32*, i32** [[DOTGLOBAL_TID__ADDR]], align 4 |
| // CHECK13-NEXT: [[TMP22:%.*]] = load i32, i32* [[TMP21]], align 4 |
| // CHECK13-NEXT: call void @__kmpc_for_static_fini(%struct.ident_t* @[[GLOB1]], i32 [[TMP22]]) |
| // CHECK13-NEXT: br label [[OMP_PRECOND_END]] |
| // CHECK13: omp.precond.end: |
| // CHECK13-NEXT: ret void |
| // |