| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=x86_64-- -mattr=+avx512f -o - %s -run-pass=postrapseudos -verify-machineinstrs | FileCheck %s |
| |
| # Test that we emit VPXORD with ZMM registers instead of YMM |
| # registers when we do not have VLX. |
| |
| --- | |
| ; ModuleID = 'test.ll' |
| source_filename = "test.ll" |
| target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" |
| target triple = "x86_64-unknown-linux-gnu" |
| |
| @tst_ = common global [4 x i64] zeroinitializer, align 64 |
| |
| define void @main() #0 { |
| bb0: |
| %gep1 = bitcast [4 x i64]* @tst_ to [4 x i64]* |
| %lsr.iv1 = bitcast [4 x i64]* %gep1 to <4 x i64>* |
| store <4 x i64> zeroinitializer, <4 x i64>* %lsr.iv1, align 16 |
| ret void |
| } |
| |
| attributes #0 = { "target-features"="+avx512f" } |
| |
| ... |
| --- |
| name: main |
| alignment: 16 |
| exposesReturnsTwice: false |
| legalized: false |
| regBankSelected: false |
| selected: false |
| failedISel: false |
| tracksRegLiveness: true |
| hasWinCFI: false |
| registers: [] |
| liveins: [] |
| frameInfo: |
| isFrameAddressTaken: false |
| isReturnAddressTaken: false |
| hasStackMap: false |
| hasPatchPoint: false |
| stackSize: 0 |
| offsetAdjustment: 0 |
| maxAlignment: 0 |
| adjustsStack: false |
| hasCalls: false |
| stackProtector: '' |
| maxCallFrameSize: 0 |
| cvBytesOfCalleeSavedRegisters: 0 |
| hasOpaqueSPAdjustment: false |
| hasVAStart: false |
| hasMustTailInVarArgFunc: false |
| localFrameSize: 0 |
| savePoint: '' |
| restorePoint: '' |
| fixedStack: [] |
| stack: [] |
| constants: [] |
| machineFunctionInfo: {} |
| body: | |
| bb.0.bb0: |
| ; CHECK-LABEL: name: main |
| ; CHECK: $zmm16 = VPXORDZrr undef $zmm16, undef $zmm16 |
| ; CHECK: VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store (s256) into %ir.lsr.iv1, align 64) |
| ; CHECK: RET 0 |
| renamable $ymm16 = AVX512_256_SET0 |
| VMOVAPSZmr $rip, 1, $noreg, @tst_, $noreg, killed renamable $zmm16 :: (store (s256) into %ir.lsr.iv1, align 64) |
| RET 0 |
| |
| ... |