| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-prelegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s |
| # RUN: llc -march=amdgcn -mcpu=fiji -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck %s |
| |
| --- |
| name: test_fminnum |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fminnum |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FMAXNUM:%[0-9]+]]:_(s32) = G_FMAXNUM [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FMINNUM %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fmaxnum |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fmaxnum |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FMAXNUM %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fminnum_ieee |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fminnum_ieee |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FMAXNUM_IEEE:%[0-9]+]]:_(s32) = G_FMAXNUM_IEEE [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMAXNUM_IEEE]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FMINNUM_IEEE %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fmaxnum_ieee |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fmaxnum_ieee |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FMINNUM_IEEE:%[0-9]+]]:_(s32) = G_FMINNUM_IEEE [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMINNUM_IEEE]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FMAXNUM_IEEE %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_amdgpu_fmin_legacy |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_amdgpu_fmin_legacy |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[AMDGPU_FMAX_LEGACY:%[0-9]+]]:_(s32) = G_AMDGPU_FMAX_LEGACY [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMAX_LEGACY]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_AMDGPU_FMIN_LEGACY %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_amdgpu_fmax_legacy |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_amdgpu_fmax_legacy |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[AMDGPU_FMIN_LEGACY:%[0-9]+]]:_(s32) = G_AMDGPU_FMIN_LEGACY [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_FMIN_LEGACY]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_AMDGPU_FMAX_LEGACY %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fadd |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fadd |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[FNEG]], [[COPY1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = nsz G_FADD %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fsub |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fsub |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = nsz G_FSUB [[COPY1]], [[COPY]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FSUB]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = nsz G_FSUB %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fma |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_fma |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]] |
| ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = nsz G_FMA [[COPY]], [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMA]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = nsz G_FMA %0, %1, %2 |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| --- |
| name: test_fmad |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_fmad |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]] |
| ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = nsz G_FMAD [[COPY]], [[FNEG]], [[FNEG1]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMAD]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = nsz G_FMAD %0, %1, %2 |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| --- |
| name: test_fmul |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fmul |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FMUL %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fpext |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_fpext |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[TRUNC]] |
| ; CHECK-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT [[FNEG]](s16) |
| ; CHECK-NEXT: $vgpr0 = COPY [[FPEXT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s16) = G_TRUNC %0(s32) |
| %2:_(s32) = G_FPEXT %1(s16) |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_intrinsic_trunc |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_intrinsic_trunc |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[INTRINSIC_TRUNC:%[0-9]+]]:_(s32) = G_INTRINSIC_TRUNC [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_TRUNC]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC_TRUNC %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_frint |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_frint |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FRINT:%[0-9]+]]:_(s32) = G_FRINT [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FRINT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FRINT %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_fnearbyint |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_fnearbyint |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEARBYINT:%[0-9]+]]:_(s32) = G_FNEARBYINT [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEARBYINT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FNEARBYINT %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_intrinsic_round |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_intrinsic_round |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[INTRINSIC_ROUND:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUND [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_ROUND]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC_ROUND %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_intrinsic_roundeven |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_intrinsic_roundeven |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[INTRINSIC_ROUNDEVEN:%[0-9]+]]:_(s32) = G_INTRINSIC_ROUNDEVEN [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[INTRINSIC_ROUNDEVEN]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC_ROUNDEVEN %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_fsin |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_fsin |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FSIN:%[0-9]+]]:_(s32) = G_FSIN [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FSIN]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FSIN %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_fcanonicalize |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_fcanonicalize |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FCANONICALIZE:%[0-9]+]]:_(s32) = G_FCANONICALIZE [[FNEG]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FCANONICALIZE]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FCANONICALIZE %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_amdgcn_rcp_iflag |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_amdgcn_rcp_iflag |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[AMDGPU_RCP_IFLAG:%[0-9]+]]:_(s32) = G_AMDGPU_RCP_IFLAG [[FNEG]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[AMDGPU_RCP_IFLAG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_AMDGPU_RCP_IFLAG %0 |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_fptrunc |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1 |
| ; CHECK-LABEL: name: test_fptrunc |
| ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FPTRUNC:%[0-9]+]]:_(s32) = G_FPTRUNC [[FNEG]](s64) |
| ; CHECK-NEXT: $vgpr0 = COPY [[FPTRUNC]](s32) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s32) = G_FPTRUNC %0:_(s64) |
| %2:_(s32) = G_FNEG %1:_ |
| $vgpr0 = COPY %2:_(s32) |
| |
| ... |
| --- |
| name: test_amdgcn_rcp |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_amdgcn_rcp |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), [[FNEG]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp), %0(s32) |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_amdgcn_rcp_legacy |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_amdgcn_rcp_legacy |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), [[FNEG]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.rcp.legacy), %0(s32) |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_amdgcn_sin |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| |
| ; CHECK-LABEL: name: test_amdgcn_sin |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), [[FNEG]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.sin), %0(s32) |
| %2:_(s32) = G_FNEG %1 |
| $vgpr0 = COPY %2(s32) |
| |
| ... |
| --- |
| name: test_fmul_legacy |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fmul_legacy |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), [[COPY]](s32), [[FNEG]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmul.legacy), %0(s32), %1(s32) |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fmed3 |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_fmed3 |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FNEG2:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), [[FNEG]](s32), [[FNEG1]](s32), [[FNEG2]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fmed3), %0(s32), %1(s32), %2(s32) |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| --- |
| name: test_amdgcn_fma_legacy |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_amdgcn_fma_legacy |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FNEG1:%[0-9]+]]:_(s32) = G_FNEG [[COPY2]] |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), [[COPY]](s32), [[FNEG]](s32), [[FNEG1]](s32) |
| ; CHECK-NEXT: $vgpr0 = COPY [[INT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = nsz G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), %0(s32), %1(s32), %2(s32) |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| |
| # Don't fold fneg for fadd, fsub, fma, fmad or fma_legacy without nsz |
| --- |
| name: test_fadd_sz |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fadd_sz |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FADD:%[0-9]+]]:_(s32) = G_FADD [[COPY]], [[COPY1]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FADD]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FADD %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fsub_sz |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_fsub_sz |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FSUB:%[0-9]+]]:_(s32) = G_FSUB [[COPY]], [[COPY1]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FSUB]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FSUB %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %3(s32) |
| |
| ... |
| --- |
| name: test_fma_sz |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_fma_sz |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FMA:%[0-9]+]]:_(s32) = G_FMA [[COPY]], [[COPY1]], [[COPY2]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMA]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = G_FMA %0, %1, %2 |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| --- |
| name: test_fmad_sz |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_fmad_sz |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FMAD:%[0-9]+]]:_(s32) = G_FMAD [[COPY]], [[COPY1]], [[COPY2]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMAD]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = G_FMAD %0, %1, %2 |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| --- |
| name: test_amdgcn_fma_legacy_sz |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_amdgcn_fma_legacy_sz |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[INT:%[0-9]+]]:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), [[COPY]](s32), [[COPY1]](s32), [[COPY2]](s32) |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[INT]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.fma.legacy), %0(s32), %1(s32), %2(s32) |
| %4:_(s32) = G_FNEG %3 |
| $vgpr0 = COPY %4(s32) |
| |
| ... |
| |
| # Don't negate 0 for minnum, maxnum |
| --- |
| name: test_fminnum_zero |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: test_fminnum_zero |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0.000000e+00 |
| ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FCONSTANT float 0.000000e+00 |
| %2:_(s32) = G_FMINNUM %0:_, %1:_ |
| %3:_(s32) = G_FNEG %2:_ |
| $vgpr0 = COPY %3:_(s32) |
| |
| ... |
| |
| # On VI and above don't negate 1.0 / (0.5 * pi) |
| --- |
| name: test_fminnum_inv2pi_half |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: test_fminnum_inv2pi_half |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(s16) = G_TRUNC [[COPY]](s32) |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_FCONSTANT half 0xH3118 |
| ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s16) = G_FMINNUM [[TRUNC]], [[C]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s16) = G_FNEG [[FMINNUM]] |
| ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[FNEG]](s16) |
| ; CHECK-NEXT: $vgpr0 = COPY [[ANYEXT]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s16) = G_TRUNC %0:_(s32) |
| %2:_(s16) = G_FCONSTANT half 0xH3118 |
| %3:_(s16) = G_FMINNUM %1:_, %2:_ |
| %4:_(s16) = G_FNEG %3:_ |
| %5:_(s32) = G_ANYEXT %4:_(s16) |
| $vgpr0 = COPY %5:_(s32) |
| |
| ... |
| --- |
| name: test_fminnum_inv2pi_float |
| body: | |
| bb.0: |
| liveins: $vgpr0 |
| ; CHECK-LABEL: name: test_fminnum_inv2pi_float |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 |
| ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s32) = G_FMINNUM [[COPY]], [[C]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMINNUM]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = G_FCONSTANT float 0x3FC45F3060000000 |
| %2:_(s32) = G_FMINNUM %0:_, %1:_ |
| %3:_(s32) = G_FNEG %2:_ |
| $vgpr0 = COPY %3:_(s32) |
| |
| ... |
| --- |
| name: test_fminnum_inv2pi_double |
| body: | |
| bb.0: |
| liveins: $vgpr0_vgpr1 |
| ; CHECK-LABEL: name: test_fminnum_inv2pi_double |
| ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1 |
| ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882 |
| ; CHECK-NEXT: [[FMINNUM:%[0-9]+]]:_(s64) = G_FMINNUM [[COPY]], [[C]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s64) = G_FNEG [[FMINNUM]] |
| ; CHECK-NEXT: $vgpr0_vgpr1 = COPY [[FNEG]](s64) |
| %0:_(s64) = COPY $vgpr0_vgpr1 |
| %1:_(s64) = G_FCONSTANT double 0x3FC45F306DC9C882 |
| %2:_(s64) = G_FMINNUM %0:_, %1:_ |
| %3:_(s64) = G_FNEG %2:_ |
| $vgpr0_vgpr1 = COPY %3:_(s64) |
| |
| ... |
| |
| #Don't fold when where instruction count will not decrease. |
| --- |
| name: test_use_both |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2 |
| |
| ; CHECK-LABEL: name: test_use_both |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]] |
| ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FNEG]], [[COPY2]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) |
| ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32) |
| ; CHECK-NEXT: $vgpr2 = COPY [[FMUL1]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = G_FMUL %0, %1 |
| %4:_(s32) = G_FNEG %3 |
| %5:_(s32) = G_FMUL %4, %2 |
| $vgpr0 = COPY %3:_(s32) |
| $vgpr1 = COPY %4:_(s32) |
| $vgpr2 = COPY %5:_(s32) |
| |
| ... |
| |
| #Don't fold when where instruction count will not decrease. |
| --- |
| name: test_use_both2 |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1 |
| |
| ; CHECK-LABEL: name: test_use_both2 |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[COPY1]] |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[FMUL]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) |
| ; CHECK-NEXT: $vgpr1 = COPY [[FNEG]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = G_FMUL %0, %1 |
| %3:_(s32) = G_FNEG %2 |
| $vgpr0 = COPY %2:_(s32) |
| $vgpr1 = COPY %3:_(s32) |
| |
| ... |
| |
| --- |
| name: multiple_uses_of_fneg |
| body: | |
| bb.0: |
| liveins: $vgpr0, $vgpr1, $vgpr2, $vgpr3 |
| |
| ; CHECK-LABEL: name: multiple_uses_of_fneg |
| ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0 |
| ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1 |
| ; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2 |
| ; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $vgpr3 |
| ; CHECK-NEXT: [[FNEG:%[0-9]+]]:_(s32) = G_FNEG [[COPY1]] |
| ; CHECK-NEXT: [[FMUL:%[0-9]+]]:_(s32) = G_FMUL [[COPY]], [[FNEG]] |
| ; CHECK-NEXT: [[FMUL1:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[COPY2]] |
| ; CHECK-NEXT: [[FMUL2:%[0-9]+]]:_(s32) = G_FMUL [[FMUL]], [[COPY3]] |
| ; CHECK-NEXT: $vgpr0 = COPY [[FMUL]](s32) |
| ; CHECK-NEXT: $vgpr1 = COPY [[FMUL1]](s32) |
| ; CHECK-NEXT: $vgpr2 = COPY [[FMUL2]](s32) |
| %0:_(s32) = COPY $vgpr0 |
| %1:_(s32) = COPY $vgpr1 |
| %2:_(s32) = COPY $vgpr2 |
| %3:_(s32) = COPY $vgpr3 |
| |
| %4:_(s32) = G_FMUL %0, %1 |
| %5:_(s32) = G_FNEG %4 |
| %6:_(s32) = G_FMUL %5, %2 |
| %7:_(s32) = G_FMUL %5, %3 |
| |
| $vgpr0 = COPY %5:_(s32) |
| $vgpr1 = COPY %6:_(s32) |
| $vgpr2 = COPY %7:_(s32) |
| |
| ... |