llvm/test/CodeGen/AMDGPU/phi-vgpr-input-moveimm.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
# RUN: llc  -mtriple=amdgcn -mcpu=gfx900 -verify-machineinstrs -run-pass=si-fix-sgpr-copies -o - %s | FileCheck -check-prefix=GCN %s
---

name:            phi_moveimm_input
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: phi_moveimm_input
  ; GCN: bb.0:
  ; GCN-NEXT:   successors: %bb.1(0x80000000)
  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr1
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.1:
  ; GCN-NEXT:   successors: %bb.2(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY1]], implicit-def $scc
  ; GCN-NEXT:   S_BRANCH %bb.2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.2:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[PHI:%[0-9]+]]:sreg_32 = PHI %5, %bb.3, [[S_ADD_U32_]], %bb.1
  ; GCN-NEXT:   S_BRANCH %bb.3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.3:
  ; GCN-NEXT:   successors: %bb.2(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[S_MOV_B32_:%[0-9]+]]:sreg_32 = S_MOV_B32 0
  ; GCN-NEXT:   S_BRANCH %bb.2
  bb.0:
    successors: %bb.1
    liveins: $sgpr0, $sgpr1

    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec

    %4:sreg_32 = COPY $sgpr0
    %5:sreg_32 = COPY $sgpr1

  bb.1:
    successors: %bb.2
    %2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
    S_BRANCH %bb.2

  bb.2:
    successors: %bb.3
    %3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
    S_BRANCH %bb.3

  bb.3:
    successors: %bb.2
    %1:sreg_32 = COPY %0
    S_BRANCH %bb.2
...

---
name:            phi_moveimm_subreg_input
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: phi_moveimm_subreg_input
  ; GCN: bb.0:
  ; GCN-NEXT:   successors: %bb.1(0x80000000)
  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[V_MOV_B64_e32_:%[0-9]+]]:vreg_64 = V_MOV_B64_e32 0, implicit $exec
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:sreg_64 = COPY $sgpr0_sgpr1
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr2_sgpr3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.1:
  ; GCN-NEXT:   successors: %bb.2(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[S_ADD_U:%[0-9]+]]:sreg_64 = S_ADD_U64_PSEUDO [[COPY]], [[COPY1]], implicit-def $scc
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:vreg_64 = COPY [[S_ADD_U]], implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.2:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[V_MOV_B64_e32_]].sub0, %bb.3, [[COPY2]].sub0, %bb.1
  ; GCN-NEXT:   S_BRANCH %bb.3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.3:
  ; GCN-NEXT:   successors: %bb.2(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
  ; GCN-NEXT:   S_BRANCH %bb.2
  bb.0:
    successors: %bb.1
    liveins: $sgpr0, $sgpr1, $sgpr2, $sgpr3

    %0:vreg_64 = V_MOV_B64_e32 0, implicit $exec

    %4:sreg_64 = COPY $sgpr0_sgpr1
    %5:sreg_64 = COPY $sgpr2_sgpr3

  bb.1:
    successors: %bb.2
    %2:sreg_64 = S_ADD_U64_PSEUDO %4, %5, implicit-def $scc
    S_BRANCH %bb.2

  bb.2:
    successors: %bb.3
    %3:sreg_32 = PHI %1.sub0:sreg_64, %bb.3, %2.sub0:sreg_64, %bb.1
    S_BRANCH %bb.3

  bb.3:
    successors: %bb.2
    %1:sreg_64 = COPY %0.sub0:vreg_64
    S_BRANCH %bb.2
...

---
name:            phi_moveimm_bad_opcode_input
tracksRegLiveness: true
body:             |
  ; GCN-LABEL: name: phi_moveimm_bad_opcode_input
  ; GCN: bb.0:
  ; GCN-NEXT:   successors: %bb.1(0x80000000)
  ; GCN-NEXT:   liveins: $sgpr0, $sgpr1, $vgpr0
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
  ; GCN-NEXT:   [[V_MOV_B32_sdwa:%[0-9]+]]:vgpr_32 = V_MOV_B32_sdwa 0, [[COPY]], 0, 5, 2, 4, implicit $exec, implicit [[COPY]](tied-def 0)
  ; GCN-NEXT:   [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr0
  ; GCN-NEXT:   [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr1
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.1:
  ; GCN-NEXT:   successors: %bb.2(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY1]], [[COPY2]], implicit-def $scc
  ; GCN-NEXT:   [[COPY3:%[0-9]+]]:vgpr_32 = COPY [[S_ADD_U32_]], implicit $exec
  ; GCN-NEXT:   S_BRANCH %bb.2
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.2:
  ; GCN-NEXT:   successors: %bb.3(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[PHI:%[0-9]+]]:vgpr_32 = PHI [[V_MOV_B32_sdwa]], %bb.3, [[COPY3]], %bb.1
  ; GCN-NEXT:   S_BRANCH %bb.3
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT: bb.3:
  ; GCN-NEXT:   successors: %bb.2(0x80000000)
  ; GCN-NEXT: {{  $}}
  ; GCN-NEXT:   [[DEF:%[0-9]+]]:sreg_32 = IMPLICIT_DEF
  ; GCN-NEXT:   S_BRANCH %bb.2
  bb.0:
    successors: %bb.1
    liveins: $sgpr0, $sgpr1, $vgpr0
    %6:vgpr_32 = COPY $vgpr0
    %0:vgpr_32 = V_MOV_B32_sdwa 0, %6:vgpr_32, 0, 5, 2, 4,  implicit $exec, implicit %6:vgpr_32(tied-def 0)

    %4:sreg_32 = COPY $sgpr0
    %5:sreg_32 = COPY $sgpr1

  bb.1:

    successors: %bb.2
    %2:sreg_32 = S_ADD_U32 %4, %5, implicit-def $scc
    S_BRANCH %bb.2
  bb.2:
    successors: %bb.3
    %3:sreg_32 = PHI %1, %bb.3, %2, %bb.1
    S_BRANCH %bb.3
  bb.3:
    successors: %bb.2
    %1:sreg_32 = COPY %0
    S_BRANCH %bb.2
...