llvm/test/CodeGen/AMDGPU/no-fold-accvgpr-mov.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx942 %s -o - | FileCheck %s --check-prefixes=GFX942
; RUN: llc -mtriple=amdgcn--amdhsa -mcpu=gfx908 %s -o - | FileCheck %s --check-prefixes=GFX908

define amdgpu_kernel void @matmul_kernel(i32 %a0, i32 %a1) {
; GFX942-LABEL: matmul_kernel:
; GFX942:       ; %bb.0: ; %entry
; GFX942-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x0
; GFX942-NEXT:    v_mov_b32_e32 v0, 0
; GFX942-NEXT:    v_accvgpr_write_b32 a2, v0
; GFX942-NEXT:    s_mov_b32 s2, 0
; GFX942-NEXT:    v_accvgpr_write_b32 a1, 0
; GFX942-NEXT:    s_waitcnt lgkmcnt(0)
; GFX942-NEXT:    s_cmp_lg_u32 s0, 0
; GFX942-NEXT:    s_cselect_b64 s[0:1], -1, 0
; GFX942-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX942-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v0
; GFX942-NEXT:    s_mov_b32 s3, 0
; GFX942-NEXT:    s_branch .LBB0_2
; GFX942-NEXT:  .LBB0_1: ; %bb2
; GFX942-NEXT:    ; in Loop: Header=BB0_2 Depth=1
; GFX942-NEXT:    s_or_b32 s4, s3, 1
; GFX942-NEXT:    s_ashr_i32 s5, s3, 31
; GFX942-NEXT:    s_mov_b32 s3, s2
; GFX942-NEXT:    v_mov_b64_e32 v[2:3], s[2:3]
; GFX942-NEXT:    v_accvgpr_mov_b32 a0, a2
; GFX942-NEXT:    v_accvgpr_mov_b32 a2, a1
; GFX942-NEXT:    v_accvgpr_mov_b32 a3, a1
; GFX942-NEXT:    s_and_b32 s3, s5, s4
; GFX942-NEXT:    s_nop 0
; GFX942-NEXT:    v_mfma_f32_16x16x16_f16 a[2:5], v[2:3], v[2:3], a[0:3]
; GFX942-NEXT:    s_cbranch_execz .LBB0_4
; GFX942-NEXT:  .LBB0_2: ; %bb
; GFX942-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX942-NEXT:    s_and_b64 vcc, exec, s[0:1]
; GFX942-NEXT:    s_cbranch_vccz .LBB0_1
; GFX942-NEXT:  ; %bb.3:
; GFX942-NEXT:    ; implicit-def: $sgpr3
; GFX942-NEXT:    ; implicit-def: $agpr2
; GFX942-NEXT:  .LBB0_4: ; %common.ret
; GFX942-NEXT:    s_endpgm
;
; GFX908-LABEL: matmul_kernel:
; GFX908:       ; %bb.0: ; %entry
; GFX908-NEXT:    s_load_dwordx2 s[0:1], s[8:9], 0x0
; GFX908-NEXT:    v_mov_b32_e32 v0, 0
; GFX908-NEXT:    v_accvgpr_write_b32 a1, 0
; GFX908-NEXT:    s_mov_b32 s2, 0
; GFX908-NEXT:    v_accvgpr_write_b32 a2, v0
; GFX908-NEXT:    s_waitcnt lgkmcnt(0)
; GFX908-NEXT:    s_cmp_lg_u32 s0, 0
; GFX908-NEXT:    s_cselect_b64 s[0:1], -1, 0
; GFX908-NEXT:    v_cndmask_b32_e64 v0, 0, 1, s[0:1]
; GFX908-NEXT:    v_cmp_ne_u32_e64 s[0:1], 1, v0
; GFX908-NEXT:    s_mov_b32 s3, 0
; GFX908-NEXT:    s_branch .LBB0_2
; GFX908-NEXT:  .LBB0_1: ; %bb2
; GFX908-NEXT:    ; in Loop: Header=BB0_2 Depth=1
; GFX908-NEXT:    s_or_b32 s4, s3, 1
; GFX908-NEXT:    s_ashr_i32 s5, s3, 31
; GFX908-NEXT:    s_mov_b32 s3, s2
; GFX908-NEXT:    v_mov_b32_e32 v1, s2
; GFX908-NEXT:    s_nop 2
; GFX908-NEXT:    v_accvgpr_read_b32 v0, a2
; GFX908-NEXT:    v_mov_b32_e32 v2, s3
; GFX908-NEXT:    v_accvgpr_read_b32 v4, a1
; GFX908-NEXT:    v_accvgpr_read_b32 v3, a1
; GFX908-NEXT:    v_accvgpr_write_b32 a0, v0
; GFX908-NEXT:    v_accvgpr_write_b32 a2, v4
; GFX908-NEXT:    v_accvgpr_write_b32 a3, v3
; GFX908-NEXT:    s_and_b32 s3, s5, s4
; GFX908-NEXT:    v_mfma_f32_16x16x16f16 a[2:5], v[1:2], v[1:2], a[0:3]
; GFX908-NEXT:    s_cbranch_execz .LBB0_4
; GFX908-NEXT:  .LBB0_2: ; %bb
; GFX908-NEXT:    ; =>This Inner Loop Header: Depth=1
; GFX908-NEXT:    s_and_b64 vcc, exec, s[0:1]
; GFX908-NEXT:    s_cbranch_vccz .LBB0_1
; GFX908-NEXT:  ; %bb.3:
; GFX908-NEXT:    ; implicit-def: $sgpr3
; GFX908-NEXT:    ; implicit-def: $agpr2
; GFX908-NEXT:  .LBB0_4: ; %common.ret
; GFX908-NEXT:    s_endpgm
entry:
  br label %bb

bb:
  %i = phi { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } [ %i10, %bb2 ], [ zeroinitializer, %entry ]
  %i1 = phi i32 [ %i5, %bb2 ], [ 0, %entry ]
  %c0 = icmp ne i32 %a0, 0
  br i1 %c0, label %bb2, label %bb11

bb2:
  %i3 = or i32 %i1, 1
  %i4 = icmp slt i32 %i1, 0
  %i5 = select i1 %i4, i32 %i3, i32 0
  %i6 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 123
  %i7 = insertelement <4 x float> zeroinitializer, float %i6, i32 0
  %i8 = call <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, <4 x float> %i7, i32 0, i32 0, i32 0)
  %i9 = extractelement <4 x float> %i8, i32 0
  %i10 = insertvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } zeroinitializer, float %i9, 123
  br label %bb

bb11:
  %c1 = icmp ne i32 %a1, 0
  br i1 %c1, label %bb12, label %common.ret

common.ret:
  ret void

bb12:
  %i13 = extractvalue { float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float, float } %i, 0
  %i14 = insertelement <4 x float> zeroinitializer, float %i13, i32 0
  %i15 = insertelement <4 x float> %i14, float 0.000000e+00, i32 0
  %i16 = insertelement <4 x float> %i15, float 0.000000e+00, i32 0
  br label %common.ret
}

; Function Attrs: convergent nocallback nofree nosync nounwind willreturn memory(none)
declare <4 x float> @llvm.amdgcn.mfma.f32.16x16x16f16(<4 x half>, <4 x half>, <4 x float>, i32 immarg, i32 immarg, i32 immarg)