llvm/test/CodeGen/AMDGPU/add_sub_u64_pseudos.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -run-pass=finalize-isel -o - %s | FileCheck -check-prefix=GFX11 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -run-pass=finalize-isel -o - %s | FileCheck -check-prefix=GFX12 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -passes=finalize-isel -o - %s | FileCheck -check-prefix=GFX11 %s
# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -passes=finalize-isel -o - %s | FileCheck -check-prefix=GFX12 %s

---
name: reg_ops
tracksRegLiveness: true
body: |
  bb.0:
    ; GFX11-LABEL: name: reg_ops
    ; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX11-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
    ; GFX11-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub0
    ; GFX11-NEXT: [[COPY3:%[0-9]+]]:sreg_32 = COPY [[DEF1]].sub1
    ; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], [[COPY2]], implicit-def $scc
    ; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], [[COPY3]], implicit-def $scc, implicit $scc
    ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ;
    ; GFX12-LABEL: name: reg_ops
    ; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX12-NEXT: [[DEF1:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 [[DEF]], [[DEF1]]
    %0:sreg_64 = IMPLICIT_DEF
    %1:sreg_64 = IMPLICIT_DEF
    %2:sreg_64 = S_ADD_U64_PSEUDO %0, %1, implicit-def $scc
...

---
name: lhs_imm
tracksRegLiveness: true
body: |
  bb.0:
    ; GFX11-LABEL: name: lhs_imm
    ; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
    ; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 6565, [[COPY]], implicit-def $scc
    ; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 0, [[COPY1]], implicit-def $scc, implicit $scc
    ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ;
    ; GFX12-LABEL: name: lhs_imm
    ; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 6565, [[DEF]]
    %0:sreg_64 = IMPLICIT_DEF
    %1:sreg_64 = S_ADD_U64_PSEUDO 6565, %0, implicit-def $scc
...

---
name: rhs_imm
tracksRegLiveness: true
body: |
  bb.0:
    ; GFX11-LABEL: name: rhs_imm
    ; GFX11: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX11-NEXT: [[COPY:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub0
    ; GFX11-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY [[DEF]].sub1
    ; GFX11-NEXT: [[S_ADD_U32_:%[0-9]+]]:sreg_32 = S_ADD_U32 [[COPY]], 6565, implicit-def $scc
    ; GFX11-NEXT: [[S_ADDC_U32_:%[0-9]+]]:sreg_32 = S_ADDC_U32 [[COPY1]], 0, implicit-def $scc, implicit $scc
    ; GFX11-NEXT: [[REG_SEQUENCE:%[0-9]+]]:sreg_64 = REG_SEQUENCE [[S_ADD_U32_]], %subreg.sub0, [[S_ADDC_U32_]], %subreg.sub1
    ;
    ; GFX12-LABEL: name: rhs_imm
    ; GFX12: [[DEF:%[0-9]+]]:sreg_64 = IMPLICIT_DEF
    ; GFX12-NEXT: [[S_ADD_U64_:%[0-9]+]]:sreg_64 = S_ADD_U64 [[DEF]], 6565
    %0:sreg_64 = IMPLICIT_DEF
    %1:sreg_64 = S_ADD_U64_PSEUDO %0, 6565, implicit-def $scc
...