llvm/test/CodeGen/RISCV/pr96366.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

declare void @use(i32)

define i32 @f(i32 %x) nounwind {
; CHECK-LABEL: f:
; CHECK:       # %bb.0:
; CHECK-NEXT:    addi sp, sp, -16
; CHECK-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
; CHECK-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
; CHECK-NEXT:    mv s0, a0
; CHECK-NEXT:    negw a0, a0
; CHECK-NEXT:    call use
; CHECK-NEXT:    li a0, 4
; CHECK-NEXT:    subw a0, a0, s0
; CHECK-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
; CHECK-NEXT:    addi sp, sp, 16
; CHECK-NEXT:    ret
  %sub1 = sub nuw i32 0, %x
  call void @use(i32 %sub1)
  %sub2 = sub i32 1, %x
  %sub3 = sub i32 3, %x
  %mul = mul i32 %x, 1
  %add1 = add i32 %sub2, %mul
  %add2 = add i32 %add1, %sub3
  ret i32 %add2
}