| commit | 6f92339d9e764d8a8452f82eff690d8ef9070ac6 | [log] [tgz] |
|---|---|---|
| author | Florian Hahn <flo@fhahn.com> | Tue Apr 08 20:52:50 2025 +0100 |
| committer | GitHub <noreply@github.com> | Tue Apr 08 20:52:50 2025 +0100 |
| tree | 39252dd077846a0cba23cf32f0d40118f2760547 | |
| parent | 556fb4c9afb1e90415239fe3fb9c6e39af8ddc03 [diff] |
[LV] Compute register usage for interleaving on VPlan. (#126437) Add a version of calculateRegisterUsage that works estimates register usage for a VPlan. This mostly just ports the existing code, with some updates to figure out what recipes will generate vectors vs scalars. There are number of changes in the computed register usages, but they should be more accurate w.r.t. to the generated vector code. There are the following changes: * Scalar usage increases in most cases by 1, as we always create a scalar canonical IV, which is alive across the loop and is not considered by the legacy implementation * Output is ordered by insertion, now scalar registers are added first due the canonical IV phi. * Using the VPlan, we now also more precisely know if an induction will be vectorized or scalarized. Depends on https://github.com/llvm/llvm-project/pull/126415 PR: https://github.com/llvm/llvm-project/pull/126437
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