tree 39252dd077846a0cba23cf32f0d40118f2760547
parent 556fb4c9afb1e90415239fe3fb9c6e39af8ddc03
author Florian Hahn <flo@fhahn.com> 1744141970 +0100
committer GitHub <noreply@github.com> 1744141970 +0100
gpgsig -----BEGIN PGP SIGNATURE-----
 
 wsFcBAABCAAQBQJn9X6SCRC1aQ7uu5UhlAAAtuoQAIvd4bGnAoeDy2+Yg4jRaIA/
 18+IncyFUV4qsfP94CRhUeiE8mwePvHd0HjB6gfgTR52YvaPz9oSuJ3rZuD3anWv
 xseo7HoH+J8cbyi+Gw55LezKlb79++G2mtzrV7nt6wEaBMJB9iznyKkkZ0SfI+PF
 0JFUhlqYJMpW525Xd4Oj56knr77+Rv9ec5qVsSdJTyRW6NlTy6RMiD42Xi+EnnZB
 3UzyKyYvy6OY1G+6n9bIgAD/dapYjRwUOM9as2MbgkSVt+5Age2oVmOYLFT9Ne3F
 qgoZu4maKqRiTk+ovvLgiLImGLxxPK5ecq6bF4OFryVy8XyLnUMmxoWP/x5RjWDO
 PKbaR97hSgb3QXJVQwd3MsFkZLGal5Yawi8/Xj25sHwpqQNMepE91HqL7uHi3tZg
 cXfent0Cz61epOvP9yRtxRqrwC3WwnzOfda3Ctw3bbq9HhLjZr3MsTFAwgNUG5CW
 5Dx0D/n/9ArzPlGx3zeVkg2NG2KG4NxX82N21AvPd16jujzMdDYAzFxYNzWBf9yD
 IQ/fPhCsW/s286ipKMyW26bcNgwlc1JHWd4Xl/CqE8IOYFvZMLIAdc6PmwRA8MG0
 ea+/a9/VJXwihVEbTJzstdXHmKOSfiNCesHtkjPaXPZHp0eLfYDCXaJpm8tkDja4
 64EZC+21uAzlTbBj5q4M
 =YX5k
 -----END PGP SIGNATURE-----
 

[LV] Compute register usage for interleaving on VPlan. (#126437)

Add a version of calculateRegisterUsage that works estimates register
usage for a VPlan. This mostly just ports the existing code, with some
updates to figure out what recipes will generate vectors vs scalars.

There are number of changes in the computed register usages, but they
should be more accurate w.r.t. to the generated vector code.

There are the following changes:

 * Scalar usage increases in most cases by 1, as we always create a
   scalar canonical IV, which is alive across the loop and is not
   considered by the legacy implementation

 * Output is ordered by insertion, now scalar registers are added first
   due the canonical IV phi.

 * Using the VPlan, we now also more precisely know if an induction will
   be vectorized or scalarized.

Depends on https://github.com/llvm/llvm-project/pull/126415

PR: https://github.com/llvm/llvm-project/pull/126437