llvm/test/CodeGen/RISCV/load-setcc-combine.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s

define i8 @zext_nonneg_load_i16(ptr %x, ptr %y) {
; CHECK-LABEL: zext_nonneg_load_i16:
; CHECK:       # %bb.0:
; CHECK-NEXT:    lh a0, 0(a0)
; CHECK-NEXT:    bltz a0, .LBB0_2
; CHECK-NEXT:  # %bb.1: # %cont
; CHECK-NEXT:    add a0, a1, a0
; CHECK-NEXT:    lbu a0, 0(a0)
; CHECK-NEXT:    ret
; CHECK-NEXT:  .LBB0_2: # %exit
; CHECK-NEXT:    li a0, 0
; CHECK-NEXT:    ret
  %a = load i16, ptr %x
  %b = icmp slt i16 %a, 0
  br i1 %b, label %exit, label %cont

cont:
  %c = zext nneg i16 %a to i64
  %d = getelementptr i8, ptr %y, i64 %c
  %e = load i8, ptr %d
  ret i8 %e

exit:
  ret i8 0
}