[RISCV] Add support for Zibi experimental extension in RISCVRedundantCopyElimination (#174920)

This patch is like what Xqcibi did in https://github.com/llvm/llvm-project/pull/174358.

llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp

diff --git a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
index 291af61..ccdeb22 100644
--- a/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
+++ b/llvm/lib/Target/RISCV/RISCVRedundantCopyElimination.cpp
@@ -20,9 +20,8 @@
 // This pass should be run after register allocation and is based on the
 // earliest versions of AArch64RedundantCopyElimination.
 //
-// FIXME: Support compares with non-zero constants for the Zibi extension. Also,
-// support compare with non-zero immediates where the immediate is stored in a
-// register.
+// FIXME: Support compare with non-zero immediates where the immediate is stored
+// in a register.
 //
 //===----------------------------------------------------------------------===//
 
@@ -93,11 +92,11 @@
   assert(TBB != nullptr && "Expected branch target basic block");
   auto Opc = Cond[0].getImm();
   if ((Opc == RISCV::QC_BEQI || Opc == RISCV::QC_E_BEQI ||
-       Opc == RISCV::NDS_BEQC) &&
+       Opc == RISCV::NDS_BEQC || Opc == RISCV::BEQI) &&
       Cond[2].isImm() && Cond[2].getImm() != 0 && TBB == &MBB)
     return true;
   if ((Opc == RISCV::QC_BNEI || Opc == RISCV::QC_E_BNEI ||
-       Opc == RISCV::NDS_BNEC) &&
+       Opc == RISCV::NDS_BNEC || Opc == RISCV::BNEI) &&
       Cond[2].isImm() && Cond[2].getImm() != 0 && TBB != &MBB)
     return true;
   return false;
@@ -148,7 +147,7 @@
           RemoveMI = true;
       }
     } else {
-      // Xqcibi compare with non-zero immediate:
+      // Xqcibi, XAndesPref and Zibi compare with non-zero immediate:
       // remove redundant addi rd,x0,imm or qc.li rd,imm as applicable.
       if (MI->getOpcode() == RISCV::ADDI && MI->getOperand(0).isReg() &&
           MI->getOperand(1).isReg() && MI->getOperand(2).isImm()) {
@@ -189,6 +188,8 @@
   MachineBasicBlock::iterator CondBr = PredMBB->getFirstTerminator();
   assert((CondBr->getOpcode() == RISCV::BEQ ||
           CondBr->getOpcode() == RISCV::BNE ||
+          CondBr->getOpcode() == RISCV::BEQI ||
+          CondBr->getOpcode() == RISCV::BNEI ||
           CondBr->getOpcode() == RISCV::QC_BEQI ||
           CondBr->getOpcode() == RISCV::QC_BNEI ||
           CondBr->getOpcode() == RISCV::QC_E_BEQI ||

llvm/test/CodeGen/RISCV/redundant-copy-elim.ll

diff --git a/llvm/test/CodeGen/RISCV/redundant-copy-elim.ll b/llvm/test/CodeGen/RISCV/redundant-copy-elim.ll
new file mode 100644
index 0000000..a93514d
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/redundant-copy-elim.ll
@@ -0,0 +1,62 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32I
+; RUN: llc -mtriple=riscv32 -mattr=+experimental-zibi -verify-machineinstrs < %s \
+; RUN:   | FileCheck %s -check-prefixes=RV32IZIBI
+
+define i32 @test_beqi(i32 %a) nounwind {
+; RV32I-LABEL: test_beqi:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    li a1, 7
+; RV32I-NEXT:    bne a0, a1, .LBB0_2
+; RV32I-NEXT:  # %bb.1: # %if.end
+; RV32I-NEXT:    li a0, 7
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB0_2: # %if.then
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    ret
+;
+; RV32IZIBI-LABEL: test_beqi:
+; RV32IZIBI:       # %bb.0: # %entry
+; RV32IZIBI-NEXT:    beqi a0, 7, .LBB0_2
+; RV32IZIBI-NEXT:  # %bb.1: # %if.then
+; RV32IZIBI-NEXT:    li a0, 1
+; RV32IZIBI-NEXT:  .LBB0_2: # %if.end
+; RV32IZIBI-NEXT:    ret
+entry:
+  %cmp = icmp eq i32 %a, 7
+  br i1 %cmp, label %if.end, label %if.then
+if.then:
+  ret i32 1
+if.end:
+  ret i32 7
+}
+
+define i32 @test_bnei(i32 %a) nounwind {
+; RV32I-LABEL: test_bnei:
+; RV32I:       # %bb.0: # %entry
+; RV32I-NEXT:    li a1, 7
+; RV32I-NEXT:    beq a0, a1, .LBB1_2
+; RV32I-NEXT:  # %bb.1: # %if.end
+; RV32I-NEXT:    li a0, 1
+; RV32I-NEXT:    ret
+; RV32I-NEXT:  .LBB1_2: # %if.then
+; RV32I-NEXT:    li a0, 7
+; RV32I-NEXT:    ret
+;
+; RV32IZIBI-LABEL: test_bnei:
+; RV32IZIBI:       # %bb.0: # %entry
+; RV32IZIBI-NEXT:    beqi a0, 7, .LBB1_2
+; RV32IZIBI-NEXT:  # %bb.1: # %if.end
+; RV32IZIBI-NEXT:    li a0, 1
+; RV32IZIBI-NEXT:    ret
+; RV32IZIBI-NEXT:  .LBB1_2: # %if.then
+; RV32IZIBI-NEXT:    ret
+entry:
+  %cmp = icmp ne i32 %a, 7
+  br i1 %cmp, label %if.end, label %if.then
+if.then:
+  ret i32 7
+if.end:
+  ret i32 1
+}

llvm/test/CodeGen/RISCV/zibi.ll

diff --git a/llvm/test/CodeGen/RISCV/zibi.ll b/llvm/test/CodeGen/RISCV/zibi.ll
index 782d70b..ad1300e 100644
--- a/llvm/test/CodeGen/RISCV/zibi.ll
+++ b/llvm/test/CodeGen/RISCV/zibi.ll
@@ -99,9 +99,7 @@
 ; ZIBI-NEXT:    beqi a0, 1, .LBB5_2
 ; ZIBI-NEXT:  # %bb.1: # %f
 ; ZIBI-NEXT:    li a0, 0
-; ZIBI-NEXT:    ret
 ; ZIBI-NEXT:  .LBB5_2: # %t
-; ZIBI-NEXT:    li a0, 1
 ; ZIBI-NEXT:    ret
   %cmp = icmp eq i32 %a, 1
   br i1 %cmp, label %t, label %f, !prof !0