| ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 |
| ; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=DEFAULT %s |
| ; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=PRED %s |
| |
| target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" |
| target triple = "arm64-apple-macosx14.0.0" |
| |
| define void @cost_store_i8(ptr %dst) #0 { |
| ; DEFAULT-LABEL: define void @cost_store_i8( |
| ; DEFAULT-SAME: ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; DEFAULT-NEXT: iter.check: |
| ; DEFAULT-NEXT: [[TMP10:%.*]] = call i64 @llvm.vscale.i64() |
| ; DEFAULT-NEXT: [[TMP13:%.*]] = shl nuw i64 [[TMP10]], 2 |
| ; DEFAULT-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 101, [[TMP13]] |
| ; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] |
| ; DEFAULT: vector.main.loop.iter.check: |
| ; DEFAULT-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; DEFAULT-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 5 |
| ; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 101, [[TMP1]] |
| ; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; DEFAULT: vector.ph: |
| ; DEFAULT-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() |
| ; DEFAULT-NEXT: [[TMP5:%.*]] = shl nuw i64 [[TMP2]], 4 |
| ; DEFAULT-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP5]], 1 |
| ; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 101, [[TMP3]] |
| ; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 101, [[N_MOD_VF]] |
| ; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; DEFAULT: vector.body: |
| ; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; DEFAULT-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] |
| ; DEFAULT-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[TMP4]], i64 [[TMP5]] |
| ; DEFAULT-NEXT: store <vscale x 16 x i8> zeroinitializer, ptr [[TMP4]], align 1 |
| ; DEFAULT-NEXT: store <vscale x 16 x i8> zeroinitializer, ptr [[TMP7]], align 1 |
| ; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] |
| ; DEFAULT-NEXT: [[TMP8:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; DEFAULT-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; DEFAULT: middle.block: |
| ; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 101, [[N_VEC]] |
| ; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] |
| ; DEFAULT: vec.epilog.iter.check: |
| ; DEFAULT-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], [[TMP13]] |
| ; DEFAULT-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]] |
| ; DEFAULT: vec.epilog.ph: |
| ; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; DEFAULT-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64() |
| ; DEFAULT-NEXT: [[TMP12:%.*]] = shl nuw i64 [[TMP11]], 2 |
| ; DEFAULT-NEXT: [[N_MOD_VF2:%.*]] = urem i64 101, [[TMP12]] |
| ; DEFAULT-NEXT: [[N_VEC3:%.*]] = sub i64 101, [[N_MOD_VF2]] |
| ; DEFAULT-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] |
| ; DEFAULT: vec.epilog.vector.body: |
| ; DEFAULT-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] |
| ; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX1]] |
| ; DEFAULT-NEXT: store <vscale x 4 x i8> zeroinitializer, ptr [[TMP9]], align 1 |
| ; DEFAULT-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX1]], [[TMP12]] |
| ; DEFAULT-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT2]], [[N_VEC3]] |
| ; DEFAULT-NEXT: br i1 [[TMP14]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] |
| ; DEFAULT: vec.epilog.middle.block: |
| ; DEFAULT-NEXT: [[CMP_N6:%.*]] = icmp eq i64 101, [[N_VEC3]] |
| ; DEFAULT-NEXT: br i1 [[CMP_N6]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] |
| ; DEFAULT: vec.epilog.scalar.ph: |
| ; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC3]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] |
| ; DEFAULT-NEXT: br label [[LOOP:%.*]] |
| ; DEFAULT: loop: |
| ; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] |
| ; DEFAULT-NEXT: store i8 0, ptr [[GEP]], align 1 |
| ; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100 |
| ; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] |
| ; DEFAULT: exit: |
| ; DEFAULT-NEXT: ret void |
| ; |
| ; PRED-LABEL: define void @cost_store_i8( |
| ; PRED-SAME: ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] { |
| ; PRED-NEXT: entry: |
| ; PRED-NEXT: br label [[VECTOR_PH:%.*]] |
| ; PRED: vector.ph: |
| ; PRED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; PRED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4 |
| ; PRED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() |
| ; PRED-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP2]], 4 |
| ; PRED-NEXT: [[TMP4:%.*]] = sub i64 101, [[TMP3]] |
| ; PRED-NEXT: [[TMP5:%.*]] = icmp ugt i64 101, [[TMP3]] |
| ; PRED-NEXT: [[TMP6:%.*]] = select i1 [[TMP5]], i64 [[TMP4]], i64 0 |
| ; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 101) |
| ; PRED-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; PRED: vector.body: |
| ; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 16 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; PRED-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] |
| ; PRED-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> zeroinitializer, ptr align 1 [[TMP7]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]]) |
| ; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP1]] |
| ; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX]], i64 [[TMP6]]) |
| ; PRED-NEXT: [[TMP8:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0 |
| ; PRED-NEXT: [[TMP9:%.*]] = xor i1 [[TMP8]], true |
| ; PRED-NEXT: br i1 [[TMP9]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] |
| ; PRED: middle.block: |
| ; PRED-NEXT: br label [[EXIT:%.*]] |
| ; PRED: exit: |
| ; PRED-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %gep = getelementptr i8, ptr %dst, i64 %iv |
| store i8 0, ptr %gep, align 1 |
| %iv.next = add i64 %iv, 1 |
| %ec = icmp eq i64 %iv, 100 |
| br i1 %ec, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| define void @trunc_store(ptr %dst, ptr %src, i16 %x) #1 { |
| ; DEFAULT-LABEL: define void @trunc_store( |
| ; DEFAULT-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i16 [[X:%.*]]) #[[ATTR1:[0-9]+]] { |
| ; DEFAULT-NEXT: iter.check: |
| ; DEFAULT-NEXT: br i1 false, label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] |
| ; DEFAULT: vector.memcheck: |
| ; DEFAULT-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 1000 |
| ; DEFAULT-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 8 |
| ; DEFAULT-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]] |
| ; DEFAULT-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]] |
| ; DEFAULT-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; DEFAULT-NEXT: br i1 [[FOUND_CONFLICT]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] |
| ; DEFAULT: vector.main.loop.iter.check: |
| ; DEFAULT-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; DEFAULT-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 5 |
| ; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 1000, [[TMP1]] |
| ; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; DEFAULT: vector.ph: |
| ; DEFAULT-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() |
| ; DEFAULT-NEXT: [[TMP16:%.*]] = shl nuw i64 [[TMP2]], 4 |
| ; DEFAULT-NEXT: [[TMP3:%.*]] = shl nuw i64 [[TMP16]], 1 |
| ; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 1000, [[TMP3]] |
| ; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 1000, [[N_MOD_VF]] |
| ; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i16> poison, i16 [[X]], i64 0 |
| ; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i16> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer |
| ; DEFAULT-NEXT: [[TMP5:%.*]] = load i64, ptr [[SRC]], align 8, !alias.scope [[META6:![0-9]+]] |
| ; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <vscale x 16 x i64> poison, i64 [[TMP5]], i64 0 |
| ; DEFAULT-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <vscale x 16 x i64> [[BROADCAST_SPLATINSERT2]], <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer |
| ; DEFAULT-NEXT: [[TMP6:%.*]] = trunc <vscale x 16 x i64> [[BROADCAST_SPLAT3]] to <vscale x 16 x i8> |
| ; DEFAULT-NEXT: [[TMP13:%.*]] = trunc <vscale x 16 x i16> [[BROADCAST_SPLAT]] to <vscale x 16 x i8> |
| ; DEFAULT-NEXT: [[TMP14:%.*]] = and <vscale x 16 x i8> [[TMP6]], [[TMP13]] |
| ; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; DEFAULT: vector.body: |
| ; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; DEFAULT-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] |
| ; DEFAULT-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP4]], i64 [[TMP16]] |
| ; DEFAULT-NEXT: store <vscale x 16 x i8> [[TMP14]], ptr [[TMP4]], align 1, !alias.scope [[META9:![0-9]+]], !noalias [[META6]] |
| ; DEFAULT-NEXT: store <vscale x 16 x i8> [[TMP14]], ptr [[TMP17]], align 1, !alias.scope [[META9]], !noalias [[META6]] |
| ; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP3]] |
| ; DEFAULT-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] |
| ; DEFAULT-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] |
| ; DEFAULT: middle.block: |
| ; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 1000, [[N_VEC]] |
| ; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] |
| ; DEFAULT: vec.epilog.iter.check: |
| ; DEFAULT-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8 |
| ; DEFAULT-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF12:![0-9]+]] |
| ; DEFAULT: vec.epilog.ph: |
| ; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] |
| ; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <8 x i16> poison, i16 [[X]], i64 0 |
| ; DEFAULT-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT4]], <8 x i16> poison, <8 x i32> zeroinitializer |
| ; DEFAULT-NEXT: [[TMP8:%.*]] = load i64, ptr [[SRC]], align 8, !alias.scope [[META13:![0-9]+]] |
| ; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT7:%.*]] = insertelement <8 x i64> poison, i64 [[TMP8]], i64 0 |
| ; DEFAULT-NEXT: [[BROADCAST_SPLAT8:%.*]] = shufflevector <8 x i64> [[BROADCAST_SPLATINSERT7]], <8 x i64> poison, <8 x i32> zeroinitializer |
| ; DEFAULT-NEXT: [[TMP9:%.*]] = trunc <8 x i64> [[BROADCAST_SPLAT8]] to <8 x i8> |
| ; DEFAULT-NEXT: [[TMP7:%.*]] = trunc <8 x i16> [[BROADCAST_SPLAT5]] to <8 x i8> |
| ; DEFAULT-NEXT: [[TMP10:%.*]] = and <8 x i8> [[TMP9]], [[TMP7]] |
| ; DEFAULT-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] |
| ; DEFAULT: vec.epilog.vector.body: |
| ; DEFAULT-NEXT: [[INDEX6:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT9:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] |
| ; DEFAULT-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX6]] |
| ; DEFAULT-NEXT: store <8 x i8> [[TMP10]], ptr [[TMP11]], align 1, !alias.scope [[META16:![0-9]+]], !noalias [[META13]] |
| ; DEFAULT-NEXT: [[INDEX_NEXT9]] = add nuw i64 [[INDEX6]], 8 |
| ; DEFAULT-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT9]], 1000 |
| ; DEFAULT-NEXT: br i1 [[TMP12]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP18:![0-9]+]] |
| ; DEFAULT: vec.epilog.middle.block: |
| ; DEFAULT-NEXT: br i1 true, label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] |
| ; DEFAULT: vec.epilog.scalar.ph: |
| ; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 1000, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] |
| ; DEFAULT-NEXT: br label [[LOOP:%.*]] |
| ; DEFAULT: loop: |
| ; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; DEFAULT-NEXT: [[X_EXT:%.*]] = zext i16 [[X]] to i64 |
| ; DEFAULT-NEXT: [[L:%.*]] = load i64, ptr [[SRC]], align 8 |
| ; DEFAULT-NEXT: [[AND:%.*]] = and i64 [[L]], [[X_EXT]] |
| ; DEFAULT-NEXT: [[TRUNC:%.*]] = trunc i64 [[AND]] to i8 |
| ; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] |
| ; DEFAULT-NEXT: store i8 [[TRUNC]], ptr [[GEP]], align 1 |
| ; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1000 |
| ; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP19:![0-9]+]] |
| ; DEFAULT: exit: |
| ; DEFAULT-NEXT: ret void |
| ; |
| ; PRED-LABEL: define void @trunc_store( |
| ; PRED-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i16 [[X:%.*]]) #[[ATTR1:[0-9]+]] { |
| ; PRED-NEXT: entry: |
| ; PRED-NEXT: br label [[VECTOR_MEMCHECK:%.*]] |
| ; PRED: vector.memcheck: |
| ; PRED-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[DST]], i64 1000 |
| ; PRED-NEXT: [[SCEVGEP1:%.*]] = getelementptr i8, ptr [[SRC]], i64 8 |
| ; PRED-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP1]] |
| ; PRED-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[SCEVGEP]] |
| ; PRED-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] |
| ; PRED-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] |
| ; PRED: vector.ph: |
| ; PRED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() |
| ; PRED-NEXT: [[TMP1:%.*]] = shl nuw i64 [[TMP0]], 4 |
| ; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <vscale x 16 x i16> poison, i16 [[X]], i64 0 |
| ; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <vscale x 16 x i16> [[BROADCAST_SPLATINSERT]], <vscale x 16 x i16> poison, <vscale x 16 x i32> zeroinitializer |
| ; PRED-NEXT: [[TMP4:%.*]] = load i64, ptr [[SRC]], align 8, !alias.scope [[META3:![0-9]+]] |
| ; PRED-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <vscale x 16 x i64> poison, i64 [[TMP4]], i64 0 |
| ; PRED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <vscale x 16 x i64> [[BROADCAST_SPLATINSERT2]], <vscale x 16 x i64> poison, <vscale x 16 x i32> zeroinitializer |
| ; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 1000) |
| ; PRED-NEXT: [[TMP3:%.*]] = trunc <vscale x 16 x i64> [[BROADCAST_SPLAT3]] to <vscale x 16 x i8> |
| ; PRED-NEXT: [[TMP2:%.*]] = trunc <vscale x 16 x i16> [[BROADCAST_SPLAT]] to <vscale x 16 x i8> |
| ; PRED-NEXT: [[TMP5:%.*]] = and <vscale x 16 x i8> [[TMP3]], [[TMP2]] |
| ; PRED-NEXT: br label [[VECTOR_BODY:%.*]] |
| ; PRED: vector.body: |
| ; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <vscale x 16 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] |
| ; PRED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDEX]] |
| ; PRED-NEXT: call void @llvm.masked.store.nxv16i8.p0(<vscale x 16 x i8> [[TMP5]], ptr align 1 [[TMP6]], <vscale x 16 x i1> [[ACTIVE_LANE_MASK]]), !alias.scope [[META6:![0-9]+]], !noalias [[META3]] |
| ; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP1]] |
| ; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <vscale x 16 x i1> @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX_NEXT]], i64 1000) |
| ; PRED-NEXT: [[TMP7:%.*]] = extractelement <vscale x 16 x i1> [[ACTIVE_LANE_MASK_NEXT]], i32 0 |
| ; PRED-NEXT: [[TMP8:%.*]] = xor i1 [[TMP7]], true |
| ; PRED-NEXT: br i1 [[TMP8]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] |
| ; PRED: middle.block: |
| ; PRED-NEXT: br label [[EXIT:%.*]] |
| ; PRED: scalar.ph: |
| ; PRED-NEXT: br label [[LOOP:%.*]] |
| ; PRED: loop: |
| ; PRED-NEXT: [[IV:%.*]] = phi i64 [ 0, [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] |
| ; PRED-NEXT: [[X_EXT:%.*]] = zext i16 [[X]] to i64 |
| ; PRED-NEXT: [[L:%.*]] = load i64, ptr [[SRC]], align 8 |
| ; PRED-NEXT: [[AND:%.*]] = and i64 [[L]], [[X_EXT]] |
| ; PRED-NEXT: [[TRUNC:%.*]] = trunc i64 [[AND]] to i8 |
| ; PRED-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] |
| ; PRED-NEXT: store i8 [[TRUNC]], ptr [[GEP]], align 1 |
| ; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 |
| ; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 1000 |
| ; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] |
| ; PRED: exit: |
| ; PRED-NEXT: ret void |
| ; |
| entry: |
| br label %loop |
| |
| loop: |
| %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] |
| %x.ext = zext i16 %x to i64 |
| %l = load i64, ptr %src, align 8 |
| %and = and i64 %l, %x.ext |
| %trunc = trunc i64 %and to i8 |
| %gep = getelementptr i8, ptr %dst, i64 %iv |
| store i8 %trunc, ptr %gep, align 1 |
| %iv.next = add i64 %iv, 1 |
| %ec = icmp eq i64 %iv.next, 1000 |
| br i1 %ec, label %exit, label %loop |
| |
| exit: |
| ret void |
| } |
| |
| attributes #0 = { "target-features"="+sve" } |
| attributes #1 = { vscale_range(1,16) "target-features"="+sve" } |
| |
| |
| ;. |
| ; DEFAULT: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| ; DEFAULT: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| ; DEFAULT: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| ; DEFAULT: [[PROF3]] = !{!"branch_weights", i32 4, i32 28} |
| ; DEFAULT: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} |
| ; DEFAULT: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} |
| ; DEFAULT: [[META6]] = !{[[META7:![0-9]+]]} |
| ; DEFAULT: [[META7]] = distinct !{[[META7]], [[META8:![0-9]+]]} |
| ; DEFAULT: [[META8]] = distinct !{[[META8]], !"LVerDomain"} |
| ; DEFAULT: [[META9]] = !{[[META10:![0-9]+]]} |
| ; DEFAULT: [[META10]] = distinct !{[[META10]], [[META8]]} |
| ; DEFAULT: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]} |
| ; DEFAULT: [[PROF12]] = !{!"branch_weights", i32 8, i32 24} |
| ; DEFAULT: [[META13]] = !{[[META14:![0-9]+]]} |
| ; DEFAULT: [[META14]] = distinct !{[[META14]], [[META15:![0-9]+]]} |
| ; DEFAULT: [[META15]] = distinct !{[[META15]], !"LVerDomain"} |
| ; DEFAULT: [[META16]] = !{[[META17:![0-9]+]]} |
| ; DEFAULT: [[META17]] = distinct !{[[META17]], [[META15]]} |
| ; DEFAULT: [[LOOP18]] = distinct !{[[LOOP18]], [[META1]], [[META2]]} |
| ; DEFAULT: [[LOOP19]] = distinct !{[[LOOP19]], [[META1]]} |
| ;. |
| ; PRED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} |
| ; PRED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} |
| ; PRED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} |
| ; PRED: [[META3]] = !{[[META4:![0-9]+]]} |
| ; PRED: [[META4]] = distinct !{[[META4]], [[META5:![0-9]+]]} |
| ; PRED: [[META5]] = distinct !{[[META5]], !"LVerDomain"} |
| ; PRED: [[META6]] = !{[[META7:![0-9]+]]} |
| ; PRED: [[META7]] = distinct !{[[META7]], [[META5]]} |
| ; PRED: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} |
| ; PRED: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} |
| ;. |
