llvm/test/Transforms/InstCombine/vector-splice.ll

; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
; RUN: opt < %s -p instcombine -S | FileCheck %s

define <4 x i32> @binop_splice_left(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_left(
; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]]
; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice1 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
  %splice2 = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v2, <4 x i32> poison, i32 %offset)
  %res = add <4 x i32> %splice1, %splice2
  ret <4 x i32> %res
}

define <4 x i32> @binop_splice_left_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_left_rhs_splat(
; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]]
; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
  %head = insertelement <4 x i32> poison, i32 %x, i32 0
  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
  %res = add <4 x i32> %splice, %splat
  ret <4 x i32> %res
}

define <4 x i32> @binop_splice_left_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_left_lhs_splat(
; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]]
; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.left.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice = call <4 x i32> @llvm.vector.splice.left(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
  %head = insertelement <4 x i32> poison, i32 %x, i32 0
  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
  %res = add <4 x i32> %splat, %splice
  ret <4 x i32> %res
}

define <4 x i32> @binop_splice_right(<4 x i32> %v1, <4 x i32> %v2, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_right(
; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[RES1:%.*]] = add <4 x i32> [[V1]], [[V2]]
; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
  %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset)
  %res = add <4 x i32> %splice1, %splice2
  ret <4 x i32> %res
}

define <4 x i32> @binop_splice_right_rhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_right_rhs_splat(
; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[RES1:%.*]] = add <4 x i32> [[V1]], [[SPLAT]]
; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
  %head = insertelement <4 x i32> poison, i32 %x, i32 0
  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
  %res = add <4 x i32> %splice, %splat
  ret <4 x i32> %res
}

define <4 x i32> @binop_splice_right_lhs_splat(<4 x i32> %v1, i32 %x, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_right_lhs_splat(
; CHECK-SAME: <4 x i32> [[V1:%.*]], i32 [[X:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[HEAD:%.*]] = insertelement <4 x i32> poison, i32 [[X]], i64 0
; CHECK-NEXT:    [[SPLAT:%.*]] = shufflevector <4 x i32> [[HEAD]], <4 x i32> poison, <4 x i32> zeroinitializer
; CHECK-NEXT:    [[RES1:%.*]] = add <4 x i32> [[SPLAT]], [[V1]]
; CHECK-NEXT:    [[RES:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[RES1]], <4 x i32> poison, i32 [[OFFSET]])
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset)
  %head = insertelement <4 x i32> poison, i32 %x, i32 0
  %splat = shufflevector <4 x i32> %head, <4 x i32> poison, <4 x i32> zeroinitializer
  %res = add <4 x i32> %splat, %splice
  ret <4 x i32> %res
}

; Negative test, mismatched offset
define <4 x i32> @binop_splice_mismatched_offset(<4 x i32> %v1, <4 x i32> %v2, i32 %offset1, i32 %offset2) {
; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_offset(
; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], i32 [[OFFSET1:%.*]], i32 [[OFFSET2:%.*]]) {
; CHECK-NEXT:    [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> poison, i32 [[OFFSET1]])
; CHECK-NEXT:    [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> poison, i32 [[OFFSET2]])
; CHECK-NEXT:    [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]]
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> poison, i32 %offset1)
  %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> poison, i32 %offset2)
  %res = add <4 x i32> %splice1, %splice2
  ret <4 x i32> %res
}

; Negative test, non poison vector operand
define <4 x i32> @binop_splice_mismatched_vector(<4 x i32> %v1, <4 x i32> %v2, <4 x i32> %v3, i32 %offset) {
; CHECK-LABEL: define <4 x i32> @binop_splice_mismatched_vector(
; CHECK-SAME: <4 x i32> [[V1:%.*]], <4 x i32> [[V2:%.*]], <4 x i32> [[V3:%.*]], i32 [[OFFSET:%.*]]) {
; CHECK-NEXT:    [[SPLICE1:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V1]], <4 x i32> [[V3]], i32 [[OFFSET]])
; CHECK-NEXT:    [[SPLICE2:%.*]] = call <4 x i32> @llvm.vector.splice.right.v4i32(<4 x i32> [[V2]], <4 x i32> [[V3]], i32 [[OFFSET]])
; CHECK-NEXT:    [[RES:%.*]] = add <4 x i32> [[SPLICE1]], [[SPLICE2]]
; CHECK-NEXT:    ret <4 x i32> [[RES]]
;
  %splice1 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v1, <4 x i32> %v3, i32 %offset)
  %splice2 = call <4 x i32> @llvm.vector.splice.right(<4 x i32> %v2, <4 x i32> %v3, i32 %offset)
  %res = add <4 x i32> %splice1, %splice2
  ret <4 x i32> %res
}