llvm/test/CodeGen/AMDGPU/cvt_rpi_i32_f32.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefix=SI-SDAG %s
; RUN: llc -mtriple=amdgcn -global-isel < %s | FileCheck -check-prefix=SI-GISEL %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 < %s | FileCheck -check-prefix=GFX11-SDAG %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -global-isel < %s | FileCheck -check-prefix=GFX11-GISEL %s

declare float @llvm.fabs.f32(float) #1
declare float @llvm.floor.f32(float) #1

define amdgpu_kernel void @cvt_rpi_i32_f32(ptr addrspace(1) %out, float %x) #0 {
; SI-SDAG-LABEL: cvt_rpi_i32_f32:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
; SI-SDAG-NEXT:    s_mov_b32 s2, -1
; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_rpi_i32_f32_e32 v0, s6
; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-SDAG-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: cvt_rpi_i32_f32:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dword s3, s[4:5], 0xb
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_rpi_i32_f32_e32 v0, s3
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32:
; GFX11-SDAG:       ; %bb.0:
; GFX11-SDAG-NEXT:    s_clause 0x1
; GFX11-SDAG-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    v_cvt_nearest_i32_f32_e32 v1, s2
; GFX11-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX11-SDAG-NEXT:    s_endpgm
;
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32:
; GFX11-GISEL:       ; %bb.0:
; GFX11-GISEL-NEXT:    s_clause 0x1
; GFX11-GISEL-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    v_cvt_nearest_i32_f32_e32 v0, s2
; GFX11-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT:    s_endpgm
  %fadd = fadd float %x, 0.5
  %floor = call nnan float @llvm.floor.f32(float %fadd) #1
  %cvt = fptosi float %floor to i32
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @cvt_rpi_i32_f32_fabs(ptr addrspace(1) %out, float %x) #0 {
; SI-SDAG-LABEL: cvt_rpi_i32_f32_fabs:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
; SI-SDAG-NEXT:    s_mov_b32 s2, -1
; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; SI-SDAG-NEXT:    v_cvt_rpi_i32_f32_e64 v0, |s6|
; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-SDAG-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: cvt_rpi_i32_f32_fabs:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dword s3, s[4:5], 0xb
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_cvt_rpi_i32_f32_e64 v0, |s3|
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32_fabs:
; GFX11-SDAG:       ; %bb.0:
; GFX11-SDAG-NEXT:    s_clause 0x1
; GFX11-SDAG-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT:    v_mov_b32_e32 v0, 0
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    v_cvt_nearest_i32_f32_e64 v1, |s2|
; GFX11-SDAG-NEXT:    global_store_b32 v0, v1, s[0:1]
; GFX11-SDAG-NEXT:    s_endpgm
;
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32_fabs:
; GFX11-GISEL:       ; %bb.0:
; GFX11-GISEL-NEXT:    s_clause 0x1
; GFX11-GISEL-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    v_cvt_nearest_i32_f32_e64 v0, |s2|
; GFX11-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT:    s_endpgm
  %x.fabs = call float @llvm.fabs.f32(float %x) #1
  %fadd = fadd float %x.fabs, 0.5
  %floor = call nnan float @llvm.floor.f32(float %fadd) #1
  %cvt = fptosi float %floor to i32
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

; FIXME: This doesn't work because it forms fsub 0.5, x
define amdgpu_kernel void @cvt_rpi_i32_f32_fneg(ptr addrspace(1) %out, float %x) #0 {
; SI-SDAG-LABEL: cvt_rpi_i32_f32_fneg:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
; SI-SDAG-NEXT:    s_mov_b32 s2, -1
; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; SI-SDAG-NEXT:    v_sub_f32_e64 v0, 0.5, s6
; SI-SDAG-NEXT:    v_cvt_flr_i32_f32_e32 v0, v0
; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-SDAG-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: cvt_rpi_i32_f32_fneg:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dword s3, s[4:5], 0xb
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_mul_f32_e64 v0, 1.0, -s3
; SI-GISEL-NEXT:    v_cvt_rpi_i32_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32_fneg:
; GFX11-SDAG:       ; %bb.0:
; GFX11-SDAG-NEXT:    s_clause 0x1
; GFX11-SDAG-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    v_sub_f32_e64 v0, 0.5, s2
; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT:    v_cvt_floor_i32_f32_e32 v0, v0
; GFX11-SDAG-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-SDAG-NEXT:    s_endpgm
;
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32_fneg:
; GFX11-GISEL:       ; %bb.0:
; GFX11-GISEL-NEXT:    s_clause 0x1
; GFX11-GISEL-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    v_max_f32_e64 v0, -s2, -s2
; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT:    v_cvt_nearest_i32_f32_e32 v0, v0
; GFX11-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT:    s_endpgm
  %x.fneg = fsub float -0.000000e+00, %x
  %fadd = fadd float %x.fneg, 0.5
  %floor = call nnan float @llvm.floor.f32(float %fadd) #1
  %cvt = fptosi float %floor to i32
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

; FIXME: This doesn't work for same reason as above
define amdgpu_kernel void @cvt_rpi_i32_f32_fabs_fneg(ptr addrspace(1) %out, float %x) #0 {
;
; SI-SDAG-LABEL: cvt_rpi_i32_f32_fabs_fneg:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
; SI-SDAG-NEXT:    s_mov_b32 s2, -1
; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; SI-SDAG-NEXT:    v_sub_f32_e64 v0, 0.5, |s6|
; SI-SDAG-NEXT:    v_cvt_flr_i32_f32_e32 v0, v0
; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-SDAG-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: cvt_rpi_i32_f32_fabs_fneg:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dword s3, s[4:5], 0xb
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_mul_f32_e64 v0, 1.0, -|s3|
; SI-GISEL-NEXT:    v_cvt_rpi_i32_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; GFX11-SDAG-LABEL: cvt_rpi_i32_f32_fabs_fneg:
; GFX11-SDAG:       ; %bb.0:
; GFX11-SDAG-NEXT:    s_clause 0x1
; GFX11-SDAG-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    v_sub_f32_e64 v0, 0.5, |s2|
; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-SDAG-NEXT:    v_cvt_floor_i32_f32_e32 v0, v0
; GFX11-SDAG-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-SDAG-NEXT:    s_endpgm
;
; GFX11-GISEL-LABEL: cvt_rpi_i32_f32_fabs_fneg:
; GFX11-GISEL:       ; %bb.0:
; GFX11-GISEL-NEXT:    s_clause 0x1
; GFX11-GISEL-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    v_max_f32_e64 v0, -|s2|, -|s2|
; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1)
; GFX11-GISEL-NEXT:    v_cvt_nearest_i32_f32_e32 v0, v0
; GFX11-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT:    s_endpgm
  %x.fabs = call float @llvm.fabs.f32(float %x) #1
  %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
  %fadd = fadd float %x.fabs.fneg, 0.5
  %floor = call nnan float @llvm.floor.f32(float %fadd) #1
  %cvt = fptosi float %floor to i32
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

define amdgpu_kernel void @no_cvt_rpi_i32_f32_0(ptr addrspace(1) %out, float %x) #0 {
; SI-SDAG-LABEL: no_cvt_rpi_i32_f32_0:
; SI-SDAG:       ; %bb.0:
; SI-SDAG-NEXT:    s_load_dword s6, s[4:5], 0xb
; SI-SDAG-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-SDAG-NEXT:    s_mov_b32 s3, 0xf000
; SI-SDAG-NEXT:    s_mov_b32 s2, -1
; SI-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; SI-SDAG-NEXT:    v_add_f32_e64 v0, s6, 0.5
; SI-SDAG-NEXT:    v_floor_f32_e32 v0, v0
; SI-SDAG-NEXT:    v_cvt_u32_f32_e32 v0, v0
; SI-SDAG-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-SDAG-NEXT:    s_endpgm
;
; SI-GISEL-LABEL: no_cvt_rpi_i32_f32_0:
; SI-GISEL:       ; %bb.0:
; SI-GISEL-NEXT:    s_load_dword s3, s[4:5], 0xb
; SI-GISEL-NEXT:    s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-GISEL-NEXT:    s_mov_b32 s2, -1
; SI-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; SI-GISEL-NEXT:    v_add_f32_e64 v0, s3, 0.5
; SI-GISEL-NEXT:    v_floor_f32_e32 v0, v0
; SI-GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
; SI-GISEL-NEXT:    s_mov_b32 s3, 0xf000
; SI-GISEL-NEXT:    buffer_store_dword v0, off, s[0:3], 0
; SI-GISEL-NEXT:    s_endpgm
;
; GFX11-SDAG-LABEL: no_cvt_rpi_i32_f32_0:
; GFX11-SDAG:       ; %bb.0:
; GFX11-SDAG-NEXT:    s_clause 0x1
; GFX11-SDAG-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-SDAG-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-SDAG-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-SDAG-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-SDAG-NEXT:    v_add_f32_e64 v0, s2, 0.5
; GFX11-SDAG-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-SDAG-NEXT:    v_floor_f32_e32 v0, v0
; GFX11-SDAG-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX11-SDAG-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-SDAG-NEXT:    s_endpgm
;
; GFX11-GISEL-LABEL: no_cvt_rpi_i32_f32_0:
; GFX11-GISEL:       ; %bb.0:
; GFX11-GISEL-NEXT:    s_clause 0x1
; GFX11-GISEL-NEXT:    s_load_b32 s2, s[4:5], 0x2c
; GFX11-GISEL-NEXT:    s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-GISEL-NEXT:    v_mov_b32_e32 v1, 0
; GFX11-GISEL-NEXT:    s_waitcnt lgkmcnt(0)
; GFX11-GISEL-NEXT:    v_add_f32_e64 v0, s2, 0.5
; GFX11-GISEL-NEXT:    s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-GISEL-NEXT:    v_floor_f32_e32 v0, v0
; GFX11-GISEL-NEXT:    v_cvt_u32_f32_e32 v0, v0
; GFX11-GISEL-NEXT:    global_store_b32 v1, v0, s[0:1]
; GFX11-GISEL-NEXT:    s_endpgm
  %fadd = fadd float %x, 0.5
  %floor = call nnan float @llvm.floor.f32(float %fadd) #1
  %cvt = fptoui float %floor to i32
  store i32 %cvt, ptr addrspace(1) %out
  ret void
}

attributes #0 = { nounwind }
attributes #1 = { nounwind readnone }