llvm/test/CodeGen/AArch64/sve-intrinsics-pred-operations.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sve < %s | FileCheck %s
; RUN: llc -mtriple=aarch64-linux-gnu -mattr=+sme -force-streaming < %s | FileCheck %s

;
; AND
;

define <vscale x 16 x i1> @and_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: and_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    and p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.and.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a,
                                                                 <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; BIC
;

define <vscale x 16 x i1> @bic_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: bic_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    bic p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.bic.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a,
                                                                 <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; BRKA
;

define <vscale x 16 x i1> @brka_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: brka_m_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brka p0.b, p1/m, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.nxv16i1(<vscale x 16 x i1> %inactive,
                                                                <vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i1> %a)
  ret <vscale x 16 x i1> %res
}

define <vscale x 16 x i1> @brka_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: brka_z_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brka p0.b, p0/z, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brka.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                  <vscale x 16 x i1> %a)
  ret <vscale x 16 x i1> %res
}

;
; BRKB
;

define <vscale x 16 x i1> @brkb_m_b8(<vscale x 16 x i1> %inactive, <vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: brkb_m_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brkb p0.b, p1/m, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.nxv16i1(<vscale x 16 x i1> %inactive,
                                                                <vscale x 16 x i1> %pg,
                                                                <vscale x 16 x i1> %a)
  ret <vscale x 16 x i1> %res
}

define <vscale x 16 x i1> @brkb_z_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: brkb_z_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brkb p0.b, p0/z, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkb.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                  <vscale x 16 x i1> %a)
  ret <vscale x 16 x i1> %res
}

;
; BRKN
;

define <vscale x 16 x i1> @brkn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkn_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brkn p2.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    mov p0.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkn.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                  <vscale x 16 x i1> %a,
                                                                  <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res
}

;
; BRKPA
;

define <vscale x 16 x i1> @brkpa_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkpa_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brkpa p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpa.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                   <vscale x 16 x i1> %a,
                                                                   <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res
}

;
; BRKPB
;

define <vscale x 16 x i1> @brkpb_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: brkpb_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    brkpb p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.brkpb.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                   <vscale x 16 x i1> %a,
                                                                   <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res
}

;
; EOR
;

define <vscale x 16 x i1> @eor_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: eor_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    eor p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.eor.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a,
                                                                 <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; ORN
;

define <vscale x 16 x i1> @orn_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: orn_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    orn p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.orn.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a,
                                                                 <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; ORR
;

define <vscale x 16 x i1> @orr_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: orr_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    orr p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.orr.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a,
                                                                 <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; NAND
;

define <vscale x 16 x i1> @nand_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: nand_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    nand p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.nand.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                  <vscale x 16 x i1> %a,
                                                                  <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; NOR
;

define <vscale x 16 x i1> @nor_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a, <vscale x 16 x i1> %b) {
; CHECK-LABEL: nor_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    nor p0.b, p0/z, p1.b, p2.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.nor.z.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a,
                                                                 <vscale x 16 x i1> %b)
  ret <vscale x 16 x i1> %res;
}

;
; PFIRST
;

define <vscale x 16 x i1> @pfirst_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: pfirst_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pfirst p1.b, p0, p1.b
; CHECK-NEXT:    mov p0.b, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.pfirst.nxv16i1(<vscale x 16 x i1> %pg,
                                                                  <vscale x 16 x i1> %a)
  ret <vscale x 16 x i1> %res
}

;
; PNEXT
;

define <vscale x 16 x i1> @pnext_b8(<vscale x 16 x i1> %pg, <vscale x 16 x i1> %a) {
; CHECK-LABEL: pnext_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pnext p1.b, p0, p1.b
; CHECK-NEXT:    mov p0.b, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 16 x i1> @llvm.aarch64.sve.pnext.nxv16i1(<vscale x 16 x i1> %pg,
                                                                 <vscale x 16 x i1> %a)
  ret <vscale x 16 x i1> %res
}

define <vscale x 8 x i1> @pnext_b16(<vscale x 8 x i1> %pg, <vscale x 8 x i1> %a) {
; CHECK-LABEL: pnext_b16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pnext p1.h, p0, p1.h
; CHECK-NEXT:    mov p0.b, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i1> @llvm.aarch64.sve.pnext.nxv8i1(<vscale x 8 x i1> %pg,
                                                               <vscale x 8 x i1> %a)
  ret <vscale x 8 x i1> %res
}

define <vscale x 4 x i1> @pnext_b32(<vscale x 4 x i1> %pg, <vscale x 4 x i1> %a) {
; CHECK-LABEL: pnext_b32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pnext p1.s, p0, p1.s
; CHECK-NEXT:    mov p0.b, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i1> @llvm.aarch64.sve.pnext.nxv4i1(<vscale x 4 x i1> %pg,
                                                               <vscale x 4 x i1> %a)
  ret <vscale x 4 x i1> %res
}

define <vscale x 2 x i1> @pnext_b64(<vscale x 2 x i1> %pg, <vscale x 2 x i1> %a) {
; CHECK-LABEL: pnext_b64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    pnext p1.d, p0, p1.d
; CHECK-NEXT:    mov p0.b, p1.b
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i1> @llvm.aarch64.sve.pnext.nxv2i1(<vscale x 2 x i1> %pg,
                                                               <vscale x 2 x i1> %a)
  ret <vscale x 2 x i1> %res
}

;
; PUNPKHI
;

define <vscale x 8 x i1> @punpkhi_b16(<vscale x 16 x i1> %a) {
; CHECK-LABEL: punpkhi_b16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpkhi p0.h, p0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i1> @llvm.aarch64.sve.punpkhi.nxv8i1(<vscale x 16 x i1> %a)
  ret <vscale x 8 x i1> %res
}

define <vscale x 4 x i1> @punpkhi_b8(<vscale x 8 x i1> %a) {
; CHECK-LABEL: punpkhi_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpkhi p0.h, p0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i1> @llvm.aarch64.sve.punpkhi.nxv4i1(<vscale x 8 x i1> %a)
  ret <vscale x 4 x i1> %res
}

define <vscale x 2 x i1> @punpkhi_b4(<vscale x 4 x i1> %a) {
; CHECK-LABEL: punpkhi_b4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpkhi p0.h, p0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i1> @llvm.aarch64.sve.punpkhi.nxv2i1(<vscale x 4 x i1> %a)
  ret <vscale x 2 x i1> %res
}

;
; PUNPKLO
;

define <vscale x 8 x i1> @punpklo_b16(<vscale x 16 x i1> %a) {
; CHECK-LABEL: punpklo_b16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpklo p0.h, p0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 8 x i1> @llvm.aarch64.sve.punpklo.nxv8i1(<vscale x 16 x i1> %a)
  ret <vscale x 8 x i1> %res
}

define <vscale x 4 x i1> @punpklo_b8(<vscale x 8 x i1> %a) {
; CHECK-LABEL: punpklo_b8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpklo p0.h, p0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 4 x i1> @llvm.aarch64.sve.punpklo.nxv4i1(<vscale x 8 x i1> %a)
  ret <vscale x 4 x i1> %res
}

define <vscale x 2 x i1> @punpklo_b4(<vscale x 4 x i1> %a) {
; CHECK-LABEL: punpklo_b4:
; CHECK:       // %bb.0:
; CHECK-NEXT:    punpklo p0.h, p0.b
; CHECK-NEXT:    ret
  %res = call <vscale x 2 x i1> @llvm.aarch64.sve.punpklo.nxv2i1(<vscale x 4 x i1> %a)
  ret <vscale x 2 x i1> %res
}