llvm/test/CodeGen/AArch64/cmtst-neg-and-one.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
; RUN: llc -mtriple=aarch64-none-linux-gnu -mattr=+neon -verify-machineinstrs < %s | FileCheck %s

define <16 x i8> @neg_and_one_v16i8(<16 x i8> %x) {
; CHECK-LABEL: neg_and_one_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.16b, #1
; CHECK-NEXT:    cmtst v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %and = and <16 x i8> %x, splat (i8 1)
  %neg = sub <16 x i8> zeroinitializer, %and
  ret <16 x i8> %neg
}

define <8 x i16> @neg_and_one_v8i16(<8 x i16> %x) {
; CHECK-LABEL: neg_and_one_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.8h, #1
; CHECK-NEXT:    cmtst v0.8h, v0.8h, v1.8h
; CHECK-NEXT:    ret
  %and = and <8 x i16> %x, splat (i16 1)
  %neg = sub <8 x i16> zeroinitializer, %and
  ret <8 x i16> %neg
}

define <4 x i32> @neg_and_one_v4i32(<4 x i32> %x) {
; CHECK-LABEL: neg_and_one_v4i32:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.4s, #1
; CHECK-NEXT:    cmtst v0.4s, v0.4s, v1.4s
; CHECK-NEXT:    ret
  %and = and <4 x i32> %x, splat (i32 1)
  %neg = sub <4 x i32> zeroinitializer, %and
  ret <4 x i32> %neg
}

define <2 x i64> @neg_and_one_v2i64(<2 x i64> %x) {
; CHECK-LABEL: neg_and_one_v2i64:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mov w8, #1 // =0x1
; CHECK-NEXT:    dup v1.2d, x8
; CHECK-NEXT:    cmtst v0.2d, v0.2d, v1.2d
; CHECK-NEXT:    ret
  %and = and <2 x i64> %x, splat (i64 1)
  %neg = sub <2 x i64> zeroinitializer, %and
  ret <2 x i64> %neg
}

define <2 x i128> @neg_and_one_v2i128(<2 x i128> %x) {
; CHECK-LABEL: neg_and_one_v2i128:
; CHECK:       // %bb.0:
; CHECK-NEXT:    sbfx x0, x0, #0, #1
; CHECK-NEXT:    sbfx x2, x2, #0, #1
; CHECK-NEXT:    mov x1, x0
; CHECK-NEXT:    mov x3, x2
; CHECK-NEXT:    ret
  %and = and <2 x i128> %x, splat (i128 1)
  %neg = sub <2 x i128> zeroinitializer, %and
  ret <2 x i128> %neg
}

define <16 x i8> @neg_and_two_v16i8(<16 x i8> %x) {
; CHECK-LABEL: neg_and_two_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.16b, #2
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    neg v0.16b, v0.16b
; CHECK-NEXT:    ret
  %and = and <16 x i8> %x, splat (i8 2)
  %neg = sub <16 x i8> zeroinitializer, %and
  ret <16 x i8> %neg
}

define <16 x i8> @sext_icmp_ne_and_one_v16i8(<16 x i8> %x) {
; CHECK-LABEL: sext_icmp_ne_and_one_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.16b, #1
; CHECK-NEXT:    cmtst v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    ret
  %and = and <16 x i8> %x, splat (i8 1)
  %cmp = icmp ne <16 x i8> %and, zeroinitializer
  %sext = sext <16 x i1> %cmp to <16 x i8>
  ret <16 x i8> %sext
}

define <8 x i16> @neg_and_bitcast_splat_one_v8i16(<8 x i16> %x) {
; CHECK-LABEL: neg_and_bitcast_splat_one_v8i16:
; CHECK:       // %bb.0:
; CHECK-NEXT:    movi v1.16b, #1
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    neg v0.8h, v0.8h
; CHECK-NEXT:    ret
  %and = and <8 x i16> %x, bitcast (<16 x i8> splat (i8 1) to <8 x i16>)
  %neg = sub <8 x i16> zeroinitializer, %and
  ret <8 x i16> %neg
}

define <16 x i8> @neg_and_nonsplat_v16i8(<16 x i8> %x) {
; CHECK-LABEL: neg_and_nonsplat_v16i8:
; CHECK:       // %bb.0:
; CHECK-NEXT:    adrp x8, .LCPI8_0
; CHECK-NEXT:    ldr q1, [x8, :lo12:.LCPI8_0]
; CHECK-NEXT:    and v0.16b, v0.16b, v1.16b
; CHECK-NEXT:    neg v0.16b, v0.16b
; CHECK-NEXT:    ret
  %and = and <16 x i8> %x, <i8 1, i8 0, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1, i8 1>
  %neg = sub <16 x i8> zeroinitializer, %and
  ret <16 x i8> %neg
}