llvm/test/CodeGen/AArch64/arm64-fpenv.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4
; RUN: llc -mtriple=aarch64 -mattr=+neon,+fp8 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,DIRECT
; RUN: llc -mtriple=aarch64 -mattr=+neon,+fp8 -verify-machineinstrs -aarch64-use-conditional-fpmr-write < %s | FileCheck %s --check-prefixes=CHECK,COND

define i64 @get_fpcr() #0 {
; CHECK-LABEL: get_fpcr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mrs x0, FPCR
; CHECK-NEXT:    ret
  %1 = tail call i64 @llvm.aarch64.get.fpcr()
  ret i64 %1
}

define void @set_fpcr(i64 %cr) {
; CHECK-LABEL: set_fpcr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    msr FPCR, x0
; CHECK-NEXT:    ret
  call void @llvm.aarch64.set.fpcr(i64 %cr)
  ret void
}

define i64 @get_fpsr() {
; CHECK-LABEL: get_fpsr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    mrs x0, FPSR
; CHECK-NEXT:    ret
  %1 = tail call i64 @llvm.aarch64.get.fpsr()
  ret i64 %1
}

define void @set_fpsr(i64 %sr) {
; CHECK-LABEL: set_fpsr:
; CHECK:       // %bb.0:
; CHECK-NEXT:    msr FPSR, x0
; CHECK-NEXT:    ret
  call void @llvm.aarch64.set.fpsr(i64 %sr)
  ret void
}

define void @set_fpmr(i64 %sr) {
; DIRECT-LABEL: set_fpmr:
; DIRECT:       // %bb.0:
; DIRECT-NEXT:    msr FPMR, x0
; DIRECT-NEXT:    ret
; COND-LABEL: set_fpmr:
; COND:       // %bb.0:
; COND-NEXT:    mrs x8, FPMR
; COND-NEXT:    cmp x8, x0
; COND-NEXT:    b.eq .LBB4_2
; COND-NEXT:  // %bb.1:
; COND-NEXT:    msr FPMR, x0
; COND-NEXT:  .LBB4_2:
; COND-NEXT:    ret
  call void @llvm.aarch64.set.fpmr(i64 %sr)
  ret void
}

define void @set_fpmr_then_fp8_cvt_and_store(i64 %fpmr, ptr %a, ptr %b, ptr %out) {
; DIRECT-LABEL: set_fpmr_then_fp8_cvt_and_store:
; DIRECT:       // %bb.0:
; DIRECT-NEXT:    msr FPMR, x0
; DIRECT-NEXT:    ldr d0, [x1]
; DIRECT-NEXT:    ldr d1, [x2]
; DIRECT-NEXT:    fcvtn v0.8b, v0.4h, v1.4h
; DIRECT-NEXT:    str d0, [x3]
; DIRECT-NEXT:    ret
; COND-LABEL: set_fpmr_then_fp8_cvt_and_store:
; COND:       // %bb.0:
; COND-NEXT:    mrs x8, FPMR
; COND-NEXT:    cmp x8, x0
; COND-NEXT:    b.eq .LBB5_2
; COND-NEXT:  // %bb.1:
; COND-NEXT:    msr FPMR, x0
; COND-NEXT:  .LBB5_2:
; COND-NEXT:    ldr d0, [x1]
; COND-NEXT:    ldr d1, [x2]
; COND-NEXT:    fcvtn v0.8b, v0.4h, v1.4h
; COND-NEXT:    str d0, [x3]
; COND-NEXT:    ret
  call void @llvm.aarch64.set.fpmr(i64 %fpmr)
  %va = load <4 x half>, ptr %a, align 8
  %vb = load <4 x half>, ptr %b, align 8
  %res = call <8 x i8> @llvm.aarch64.neon.fp8.fcvtn.v8i8.v4f16(<4 x half> %va, <4 x half> %vb)
  store <8 x i8> %res, ptr %out, align 8
  ret void
}

declare i64 @llvm.aarch64.get.fpcr()
declare void @llvm.aarch64.set.fpcr(i64)
declare i64 @llvm.aarch64.get.fpsr()
declare void @llvm.aarch64.set.fpsr(i64)

attributes #0 = { nounwind }