commit 6006d43e2d7dda56844f1c3867baa981cfefb8ea
author Craig Topper <craig.topper@sifive.com> Wed May 24 12:15:23 2023 -0700
committer Craig Topper <craig.topper@sifive.com> Wed May 24 12:40:10 2023 -0700
tree c6dc207cfb989a0cf1ddcb7891ec07a7b6f620c4
parent 8a8c2b2ea54bd0ab13a0b9cde32109542836a46b

LLVM_FALLTHROUGH => [[fallthrough]]. NFC

Reviewed By: MaskRay

Differential Revision: https://reviews.llvm.org/D150996

llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp

diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 31d6d97..3b10a27 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2529,7 +2529,7 @@
       return 2 * LT.first;
     if (!Ty->getScalarType()->isFP128Ty())
       return LT.first;
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case ISD::FMUL:
   case ISD::FDIV:
     // These nodes are marked as 'custom' just to lower them to SVE.

llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index c517f1b..41bdf45 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3994,7 +3994,7 @@
       if (SRLConst && SRLConst->getSExtValue() == 16)
         return false;
     }
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case ISD::ROTL:
   case ISD::SHL:
   case ISD::AND:

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 1598f4b..e9554a8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10686,7 +10686,7 @@
       RetOps.push_back(Extract);
       return DAG.getMergeValues(RetOps, dl);
     }
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   }
   case Intrinsic::ppc_vsx_disassemble_pair: {
     int NumVecs = 2;

llvm/lib/Target/PowerPC/PPCRegisterInfo.h

diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 2a2fe25..11dbbce 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -183,7 +183,7 @@
       case 'f':
         if (RegName[1] == 'p')
           return RegName + 2;
-        LLVM_FALLTHROUGH;
+        [[fallthrough]];
       case 'r':
       case 'v':
         if (RegName[1] == 's') {

llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp

diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index c2582bc..33c6aa2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -55,7 +55,7 @@
   switch (Intrinsic) {
   case Intrinsic::spv_load:
     AlignIdx = 2;
-    LLVM_FALLTHROUGH;
+    [[fallthrough]];
   case Intrinsic::spv_store: {
     if (I.getNumOperands() >= AlignIdx + 1) {
       auto *AlignOp = cast<ConstantInt>(I.getOperand(AlignIdx));