LLVM_FALLTHROUGH => [[fallthrough]]. NFC
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D150996
diff --git a/llvm/lib/Analysis/MemoryLocation.cpp b/llvm/lib/Analysis/MemoryLocation.cpp
index e839f9e..0404b32 100644
--- a/llvm/lib/Analysis/MemoryLocation.cpp
+++ b/llvm/lib/Analysis/MemoryLocation.cpp
@@ -257,7 +257,7 @@
case LibFunc_memset_chk:
assert(ArgIdx == 0 && "Invalid argument index for memset_chk");
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case LibFunc_memcpy_chk: {
assert((ArgIdx == 0 || ArgIdx == 1) &&
"Invalid argument index for memcpy_chk");
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 2ad7870..a700eae 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -15325,7 +15325,7 @@
if (RHS->getType()->isPointerTy())
return;
RHS = getUMaxExpr(RHS, One);
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case CmpInst::ICMP_SLT: {
RHS = getMinusSCEV(RHS, One);
RHS = DividesBy ? GetPreviousSCEVDividesByDivisor(RHS, DividesBy) : RHS;
diff --git a/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp b/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
index 2be72a2..a0cd8b7 100644
--- a/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
+++ b/llvm/lib/DebugInfo/LogicalView/Readers/LVBinaryReader.cpp
@@ -443,7 +443,7 @@
break;
case MCDisassembler::SoftFail:
LLVM_DEBUG({ dbgs() << "Potentially undefined instruction:"; });
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case MCDisassembler::Success: {
std::string Buffer;
raw_string_ostream Stream(Buffer);
diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
index 4b4a710..19ba9e8 100644
--- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
+++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp
@@ -2420,7 +2420,7 @@
case OMPScheduleType::BaseRuntimeSimd:
assert(!ChunkSize &&
"schedule type does not support user-defined chunk sizes");
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case OMPScheduleType::BaseDynamicChunked:
case OMPScheduleType::BaseGuidedChunked:
case OMPScheduleType::BaseGuidedIterativeChunked:
diff --git a/llvm/lib/ProfileData/InstrProf.cpp b/llvm/lib/ProfileData/InstrProf.cpp
index 1dd1ce4..749147a 100644
--- a/llvm/lib/ProfileData/InstrProf.cpp
+++ b/llvm/lib/ProfileData/InstrProf.cpp
@@ -1385,7 +1385,7 @@
case 10ull:
H.TemporalProfTracesOffset =
read(Buffer, offsetOf(&Header::TemporalProfTracesOffset));
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case 9ull:
H.BinaryIdOffset = read(Buffer, offsetOf(&Header::BinaryIdOffset));
[[fallthrough]];
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 31d6d97..3b10a27 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -2529,7 +2529,7 @@
return 2 * LT.first;
if (!Ty->getScalarType()->isFP128Ty())
return LT.first;
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case ISD::FMUL:
case ISD::FDIV:
// These nodes are marked as 'custom' just to lower them to SVE.
diff --git a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
index c517f1b..41bdf45 100644
--- a/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp
@@ -3994,7 +3994,7 @@
if (SRLConst && SRLConst->getSExtValue() == 16)
return false;
}
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case ISD::ROTL:
case ISD::SHL:
case ISD::AND:
diff --git a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
index 1598f4b..e9554a8 100644
--- a/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/llvm/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -10686,7 +10686,7 @@
RetOps.push_back(Extract);
return DAG.getMergeValues(RetOps, dl);
}
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
}
case Intrinsic::ppc_vsx_disassemble_pair: {
int NumVecs = 2;
diff --git a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
index 2a2fe25..11dbbce 100644
--- a/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/llvm/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -183,7 +183,7 @@
case 'f':
if (RegName[1] == 'p')
return RegName + 2;
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case 'r':
case 'v':
if (RegName[1] == 's') {
diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
index c2582bc..33c6aa2 100644
--- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp
@@ -55,7 +55,7 @@
switch (Intrinsic) {
case Intrinsic::spv_load:
AlignIdx = 2;
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
case Intrinsic::spv_store: {
if (I.getNumOperands() >= AlignIdx + 1) {
auto *AlignOp = cast<ConstantInt>(I.getOperand(AlignIdx));
diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
index dab4d16..ad1326c 100644
--- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
+++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp
@@ -8487,7 +8487,7 @@
Ops[1] = SafeRHS;
return new VPWidenRecipe(*I, make_range(Ops.begin(), Ops.end()));
}
- LLVM_FALLTHROUGH;
+ [[fallthrough]];
}
case Instruction::Add:
case Instruction::And:
