| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc %s -o - -run-pass=machine-sink -mtriple=arm-none-eabi | FileCheck %s |
| |
| --- | |
| target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64" |
| target triple = "arm-none-unknown-eabi" |
| |
| %struct.anon = type { i32, i32 } |
| |
| @e = external constant [2 x %struct.anon], align 4 |
| |
| define arm_aapcscc void @g(i32 * noalias %a, i32 *%b, i32 %x) { |
| entry: |
| %c = getelementptr inbounds [2 x %struct.anon], [2 x %struct.anon]* @e, i32 0, i32 %x, i32 0 |
| %l1 = load i32, i32* %c, align 4 |
| %d = getelementptr inbounds [2 x %struct.anon], [2 x %struct.anon]* @e, i32 0, i32 %x, i32 1 |
| %l2 = load i32, i32* %d, align 4 |
| br i1 undef, label %land.lhs.true, label %if.end |
| |
| land.lhs.true: ; preds = %entry |
| br label %if.end |
| |
| if.end: ; preds = %land.lhs.true, %entry |
| %h.0 = phi i32 [ %l1, %entry ], [ 0, %land.lhs.true ] |
| ret void |
| } |
| |
| ... |
| --- |
| name: g |
| tracksRegLiveness: true |
| registers: |
| - { id: 0, class: gpr, preferred-register: '' } |
| - { id: 1, class: gpr, preferred-register: '' } |
| - { id: 2, class: gpr, preferred-register: '' } |
| - { id: 6, class: gpr, preferred-register: '' } |
| - { id: 7, class: gpr, preferred-register: '' } |
| - { id: 8, class: gpr, preferred-register: '' } |
| - { id: 9, class: gprnopc, preferred-register: '' } |
| liveins: |
| - { reg: '$r0', virtual-reg: '%8' } |
| - { reg: '$r1', virtual-reg: '%9' } |
| liveins: [] |
| body: | |
| ; CHECK-LABEL: name: g |
| ; CHECK: bb.0: |
| ; CHECK: successors: %bb.1(0x40000000), %bb.3(0x40000000) |
| ; CHECK: liveins: $r0, $r1 |
| ; CHECK: [[COPY:%[0-9]+]]:gpr = COPY $r1 |
| ; CHECK: [[COPY1:%[0-9]+]]:gprnopc = COPY $r0 |
| ; CHECK: [[LDR_PRE_REG:%[0-9]+]]:gpr, [[LDR_PRE_REG1:%[0-9]+]]:gpr = LDR_PRE_REG [[COPY]], killed [[COPY1]], 16387, 14 /* CC::al */, $noreg :: (load (s32) from %ir.c) |
| ; CHECK: [[MOVi:%[0-9]+]]:gpr = MOVi 0, 14 /* CC::al */, $noreg, $noreg |
| ; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: Bcc %bb.1, 0 /* CC::eq */, $cpsr |
| ; CHECK: bb.3: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: B %bb.2 |
| ; CHECK: bb.1: |
| ; CHECK: successors: %bb.2(0x80000000) |
| ; CHECK: bb.2: |
| ; CHECK: [[PHI:%[0-9]+]]:gpr = PHI [[LDR_PRE_REG]], %bb.3, [[MOVi]], %bb.1 |
| ; CHECK: CMPri [[MOVi]], 0, 14 /* CC::al */, $noreg, implicit-def $cpsr |
| ; CHECK: [[LDRi12_:%[0-9]+]]:gpr = LDRi12 killed [[LDR_PRE_REG1]], 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.d) |
| ; CHECK: MOVPCLR 14 /* CC::al */, $noreg |
| bb.0: |
| liveins: $r0, $r1 |
| successors: %bb.1(0x40000000), %bb.2(0x40000000) |
| |
| %8:gpr = COPY $r1 |
| %9:gprnopc = COPY $r0 |
| %0:gpr, %6:gpr = LDR_PRE_REG %8, killed %9, 16387, 14, $noreg :: (load (s32) from %ir.c) |
| %7:gpr = MOVi 0, 14, $noreg, $noreg |
| CMPri %7, 0, 14, $noreg, implicit-def $cpsr |
| Bcc %bb.2, 1, $cpsr |
| B %bb.1 |
| |
| bb.1: |
| successors: %bb.2(0x80000000) |
| |
| bb.2: |
| |
| %2:gpr = PHI %0, %bb.0, %7, %bb.1 |
| CMPri %7, 0, 14, $noreg, implicit-def $cpsr |
| %1:gpr = LDRi12 killed %6, 4, 14, $noreg :: (load (s32) from %ir.d) |
| MOVPCLR 14, $noreg |
| |
| ... |