llvm/test/CodeGen/AMDGPU/GlobalISel/regbankselect-cttz-zero-undef.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-fast | FileCheck %s
# RUN: llc -march=amdgcn -mcpu=fiji -run-pass=regbankselect %s -verify-machineinstrs -o - -regbankselect-greedy | FileCheck %s

---
name: cttz_zero_undef_s32_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0
    ; CHECK-LABEL: name: cttz_zero_undef_s32_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
    ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
    %0:_(s32) = COPY $sgpr0
    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...

---
name: cttz_zero_undef_s32_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: cttz_zero_undef_s32_v
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0
    ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:vgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s32)
    ; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...

---
name: cttz_zero_undef_s64_s
legalized: true

body: |
  bb.0:
    liveins: $sgpr0_sgpr1
    ; CHECK-LABEL: name: cttz_zero_undef_s64_s
    ; CHECK: [[COPY:%[0-9]+]]:sgpr(s64) = COPY $sgpr0_sgpr1
    ; CHECK: [[CTTZ_ZERO_UNDEF:%[0-9]+]]:sgpr(s32) = G_CTTZ_ZERO_UNDEF [[COPY]](s64)
    ; CHECK: S_ENDPGM 0, implicit [[CTTZ_ZERO_UNDEF]](s32)
    %0:_(s64) = COPY $sgpr0_sgpr1
    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...

---
name: cttz_zero_undef_s64_v
legalized: true

body: |
  bb.0:
    liveins: $vgpr0_vgpr1
    ; CHECK-LABEL: name: cttz_zero_undef_s64_v
    ; CHECK: [[COPY:%[0-9]+]]:vgpr(s64) = COPY $vgpr0_vgpr1
    ; CHECK: [[UV:%[0-9]+]]:vgpr(s32), [[UV1:%[0-9]+]]:vgpr(s32) = G_UNMERGE_VALUES [[COPY]](s64)
    ; CHECK: [[AMDGPU_FFBL_B32_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV]](s32)
    ; CHECK: [[AMDGPU_FFBL_B32_1:%[0-9]+]]:vgpr(s32) = G_AMDGPU_FFBL_B32 [[UV1]](s32)
    ; CHECK: [[C:%[0-9]+]]:vgpr(s32) = G_CONSTANT i32 32
    ; CHECK: [[ADD:%[0-9]+]]:vgpr(s32) = G_ADD [[AMDGPU_FFBL_B32_1]], [[C]]
    ; CHECK: [[UMIN:%[0-9]+]]:vgpr(s32) = G_UMIN [[AMDGPU_FFBL_B32_]], [[ADD]]
    ; CHECK: S_ENDPGM 0, implicit [[UMIN]](s32)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CTTZ_ZERO_UNDEF %0
    S_ENDPGM 0, implicit %1
...