| # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py |
| # RUN: llc -mtriple=amdgcn-amd-mesa3d -mcpu=gfx1010 -run-pass=amdgpu-regbank-combiner -verify-machineinstrs %s -o - | FileCheck %s |
| |
| --- |
| name: test_min_max_ValK0_K1_i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_min_max_ValK0_K1_i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 -12 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMAX %0, %7 |
| %4:sgpr(s32) = G_CONSTANT i32 17 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMIN %3, %8 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: min_max_ValK0_K1_i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: min_max_ValK0_K1_i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 -12 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMAX %7, %0 |
| %4:sgpr(s32) = G_CONSTANT i32 17 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMIN %3, %8 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_min_K1max_ValK0__i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_min_K1max_ValK0__i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 -12 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMAX %0, %7 |
| %4:sgpr(s32) = G_CONSTANT i32 17 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMIN %8, %3 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_min_K1max_K0Val__i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_min_K1max_K0Val__i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C]], [[C1]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 -12 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMAX %7, %0 |
| %4:sgpr(s32) = G_CONSTANT i32 17 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMIN %8, %3 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_max_min_ValK1_K0_i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_max_min_ValK1_K0_i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 17 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMIN %0, %7 |
| %4:sgpr(s32) = G_CONSTANT i32 -12 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMAX %3, %8 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_max_min_K1Val_K0_i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_max_min_K1Val_K0_i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 17 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMIN %7, %0 |
| %4:sgpr(s32) = G_CONSTANT i32 -12 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMAX %3, %8 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_max_K0min_ValK1__i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_max_K0min_ValK1__i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 17 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMIN %0, %7 |
| %4:sgpr(s32) = G_CONSTANT i32 -12 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMAX %8, %3 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_max_K0min_K1Val__i32 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_max_K0min_K1Val__i32 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(s32) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[AMDGPU_SMED3_:%[0-9]+]]:vgpr(s32) = G_AMDGPU_SMED3 [[COPY]], [[C1]], [[C]] |
| ; CHECK: $vgpr0 = COPY [[AMDGPU_SMED3_]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY2]], implicit $vgpr0 |
| %0:vgpr(s32) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %2:sgpr(s32) = G_CONSTANT i32 17 |
| %7:vgpr(s32) = COPY %2(s32) |
| %3:vgpr(s32) = G_SMIN %7, %0 |
| %4:sgpr(s32) = G_CONSTANT i32 -12 |
| %8:vgpr(s32) = COPY %4(s32) |
| %5:vgpr(s32) = G_SMAX %8, %3 |
| $vgpr0 = COPY %5(s32) |
| %6:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %6, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_max_K0min_K1Val__v2i16 |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $vgpr0, $sgpr30_sgpr31 |
| |
| ; CHECK-LABEL: name: test_max_K0min_K1Val__v2i16 |
| ; CHECK: liveins: $vgpr0, $sgpr30_sgpr31 |
| ; CHECK: [[COPY:%[0-9]+]]:vgpr(<2 x s16>) = COPY $vgpr0 |
| ; CHECK: [[COPY1:%[0-9]+]]:sgpr_64 = COPY $sgpr30_sgpr31 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[BUILD_VECTOR_TRUNC:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C]](s32), [[C]](s32) |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[BUILD_VECTOR_TRUNC1:%[0-9]+]]:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC [[C1]](s32), [[C1]](s32) |
| ; CHECK: [[COPY2:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC]](<2 x s16>) |
| ; CHECK: [[SMIN:%[0-9]+]]:vgpr(<2 x s16>) = G_SMIN [[COPY2]], [[COPY]] |
| ; CHECK: [[COPY3:%[0-9]+]]:vgpr(<2 x s16>) = COPY [[BUILD_VECTOR_TRUNC1]](<2 x s16>) |
| ; CHECK: [[SMAX:%[0-9]+]]:vgpr(<2 x s16>) = G_SMAX [[COPY3]], [[SMIN]] |
| ; CHECK: $vgpr0 = COPY [[SMAX]](<2 x s16>) |
| ; CHECK: [[COPY4:%[0-9]+]]:ccr_sgpr_64 = COPY [[COPY1]] |
| ; CHECK: S_SETPC_B64_return [[COPY4]], implicit $vgpr0 |
| %0:vgpr(<2 x s16>) = COPY $vgpr0 |
| %1:sgpr_64 = COPY $sgpr30_sgpr31 |
| %9:sgpr(s32) = G_CONSTANT i32 17 |
| %2:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %9(s32), %9(s32) |
| %10:sgpr(s32) = G_CONSTANT i32 -12 |
| %5:sgpr(<2 x s16>) = G_BUILD_VECTOR_TRUNC %10(s32), %10(s32) |
| %11:vgpr(<2 x s16>) = COPY %2(<2 x s16>) |
| %4:vgpr(<2 x s16>) = G_SMIN %11, %0 |
| %12:vgpr(<2 x s16>) = COPY %5(<2 x s16>) |
| %7:vgpr(<2 x s16>) = G_SMAX %12, %4 |
| $vgpr0 = COPY %7(<2 x s16>) |
| %8:ccr_sgpr_64 = COPY %1 |
| S_SETPC_B64_return %8, implicit $vgpr0 |
| ... |
| |
| --- |
| name: test_uniform_min_max |
| legalized: true |
| regBankSelected: true |
| tracksRegLiveness: true |
| body: | |
| bb.1: |
| liveins: $sgpr2 |
| |
| ; CHECK-LABEL: name: test_uniform_min_max |
| ; CHECK: liveins: $sgpr2 |
| ; CHECK: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr2 |
| ; CHECK: [[C:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 -12 |
| ; CHECK: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[C]] |
| ; CHECK: [[C1:%[0-9]+]]:sgpr(s32) = G_CONSTANT i32 17 |
| ; CHECK: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[SMAX]], [[C1]] |
| ; CHECK: [[COPY1:%[0-9]+]]:vgpr(s32) = COPY [[SMIN]](s32) |
| ; CHECK: [[INT:%[0-9]+]]:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), [[COPY1]](s32) |
| ; CHECK: $sgpr0 = COPY [[INT]](s32) |
| ; CHECK: SI_RETURN_TO_EPILOG implicit $sgpr0 |
| %0:sgpr(s32) = COPY $sgpr2 |
| %3:sgpr(s32) = G_CONSTANT i32 -12 |
| %4:sgpr(s32) = G_SMAX %0, %3 |
| %5:sgpr(s32) = G_CONSTANT i32 17 |
| %6:sgpr(s32) = G_SMIN %4, %5 |
| %8:vgpr(s32) = COPY %6(s32) |
| %7:sgpr(s32) = G_INTRINSIC intrinsic(@llvm.amdgcn.readfirstlane), %8(s32) |
| $sgpr0 = COPY %7(s32) |
| SI_RETURN_TO_EPILOG implicit $sgpr0 |
| ... |