llvm/test/CodeGen/AMDGPU/GlobalISel/postlegalizercombiner-ubfx.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx1010 -run-pass=amdgpu-postlegalizer-combiner -verify-machineinstrs %s -o - | FileCheck --check-prefix=GCN %s

---
name:            bfe_and_lshr_s32
legalized:       true
tracksRegLiveness: true

body: |
  bb.0.entry:
  liveins: $vgpr0

    ; GCN-LABEL: name: bfe_and_lshr_s32
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 5
    ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[C1]](s32), [[C]]
    ; GCN: $vgpr0 = COPY [[UBFX]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 8
    %2:_(s32) = G_LSHR %0, %1(s32)
    %3:_(s32) = G_CONSTANT i32 31
    %4:_(s32) = G_AND %2, %3
    $vgpr0 = COPY %4(s32)

...

---
name:            bfe_and_lshr_s64
legalized:       true
tracksRegLiveness: true

body: |
  bb.0.entry:
  liveins: $vgpr0_vgpr1

    ; GCN-LABEL: name: bfe_and_lshr_s64
    ; GCN: liveins: $vgpr0_vgpr1
    ; GCN: [[COPY:%[0-9]+]]:_(s64) = COPY $vgpr0_vgpr1
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 10
    ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; GCN: [[UBFX:%[0-9]+]]:_(s64) = G_UBFX [[COPY]], [[C1]](s32), [[C]]
    ; GCN: $vgpr0_vgpr1 = COPY [[UBFX]](s64)
    %0:_(s64) = COPY $vgpr0_vgpr1
    %1:_(s32) = G_CONSTANT i32 8
    %2:_(s64) = G_LSHR %0, %1(s32)
    %3:_(s64) = G_CONSTANT i64 1023
    %4:_(s64) = G_AND %2, %3
    $vgpr0_vgpr1 = COPY %4(s64)

...

---
name:            toobig_and_lshr_s32
legalized:       true
tracksRegLiveness: true

body: |
  bb.0.entry:
  liveins: $vgpr0

    ; GCN-LABEL: name: toobig_and_lshr_s32
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 28
    ; GCN: [[LSHR:%[0-9]+]]:_(s32) = G_LSHR [[COPY]], [[C]](s32)
    ; GCN: $vgpr0 = COPY [[LSHR]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 28
    %2:_(s32) = G_LSHR %0, %1(s32)
    %3:_(s32) = G_CONSTANT i32 511
    %4:_(s32) = G_AND %2, %3
    $vgpr0 = COPY %4(s32)

...

---
name:            bfe_and_ashr_s32
legalized:       true
tracksRegLiveness: true

body: |
  bb.0.entry:
  liveins: $vgpr0

    ; GCN-LABEL: name: bfe_and_ashr_s32
    ; GCN: liveins: $vgpr0
    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 8
    ; GCN: [[ASHR:%[0-9]+]]:_(s32) = G_ASHR [[COPY]], [[C]](s32)
    ; GCN: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 31
    ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[ASHR]], [[C1]]
    ; GCN: $vgpr0 = COPY [[AND]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = G_CONSTANT i32 8
    %2:_(s32) = G_ASHR %0, %1(s32)
    %3:_(s32) = G_CONSTANT i32 31
    %4:_(s32) = G_AND %2, %3
    $vgpr0 = COPY %4(s32)

...