llvm/test/CodeGen/AMDGPU/GlobalISel/legalize-ubfx.mir

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=fiji -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck --check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx900 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck --check-prefix=GCN %s
# RUN: llc -mtriple=amdgcn-mesa-mesa3d -mcpu=gfx1010 -O0 -run-pass=legalizer -global-isel-abort=0 %s -o - | FileCheck --check-prefix=GCN %s
...
---
name:            test_ubfx_s32
body: |
  bb.0.entry:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN-LABEL: name: test_ubfx_s32
    ; GCN: %copy:_(s32) = COPY $vgpr0
    ; GCN: %offset:_(s32) = COPY $vgpr1
    ; GCN: %width:_(s32) = COPY $vgpr2
    ; GCN: %ubfx:_(s32) = G_UBFX %copy, %offset(s32), %width
    ; GCN: $vgpr0 = COPY %ubfx(s32)
    %copy:_(s32) = COPY $vgpr0
    %offset:_(s32) = COPY $vgpr1
    %width:_(s32) = COPY $vgpr2
    %ubfx:_(s32) = G_UBFX %copy, %offset(s32), %width
    $vgpr0 = COPY %ubfx(s32)
...

---
name:            test_ubfx_s64
body: |
  bb.0.entry:
    liveins: $vgpr0_vgpr1, $vgpr2, $vgpr3

    ; GCN-LABEL: name: test_ubfx_s64
    ; GCN: %copy:_(s64) = COPY $vgpr0_vgpr1
    ; GCN: %offset:_(s32) = COPY $vgpr2
    ; GCN: %width:_(s32) = COPY $vgpr3
    ; GCN: %ubfx:_(s64) = G_UBFX %copy, %offset(s32), %width
    ; GCN: $vgpr0_vgpr1 = COPY %ubfx(s64)
    %copy:_(s64) = COPY $vgpr0_vgpr1
    %offset:_(s32) = COPY $vgpr2
    %width:_(s32) = COPY $vgpr3
    %ubfx:_(s64) = G_UBFX %copy, %offset(s32), %width
    $vgpr0_vgpr1 = COPY %ubfx(s64)
...

---
name:            test_ubfx_s8
body: |
  bb.0.entry:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN-LABEL: name: test_ubfx_s8
    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 255
    ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
    ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
    ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[AND]](s32), [[AND1]]
    ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UBFX]], [[C]]
    ; GCN: $vgpr0 = COPY [[AND2]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = COPY $vgpr2
    %copy:_(s8) = G_TRUNC %0
    %offset:_(s8) = G_TRUNC %1
    %width:_(s8) = G_TRUNC %2
    %ubfx:_(s8) = G_UBFX %copy, %offset, %width
    %4:_(s32) = G_ZEXT %ubfx
    $vgpr0 = COPY %4
...

---
name:            test_ubfx_s16
body: |
  bb.0.entry:
    liveins: $vgpr0, $vgpr1, $vgpr2

    ; GCN-LABEL: name: test_ubfx_s16
    ; GCN: [[COPY:%[0-9]+]]:_(s32) = COPY $vgpr0
    ; GCN: [[COPY1:%[0-9]+]]:_(s32) = COPY $vgpr1
    ; GCN: [[COPY2:%[0-9]+]]:_(s32) = COPY $vgpr2
    ; GCN: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 65535
    ; GCN: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
    ; GCN: [[AND1:%[0-9]+]]:_(s32) = G_AND [[COPY2]], [[C]]
    ; GCN: [[UBFX:%[0-9]+]]:_(s32) = G_UBFX [[COPY]], [[AND]](s32), [[AND1]]
    ; GCN: [[AND2:%[0-9]+]]:_(s32) = G_AND [[UBFX]], [[C]]
    ; GCN: $vgpr0 = COPY [[AND2]](s32)
    %0:_(s32) = COPY $vgpr0
    %1:_(s32) = COPY $vgpr1
    %2:_(s32) = COPY $vgpr2
    %copy:_(s16) = G_TRUNC %0
    %offset:_(s16) = G_TRUNC %1
    %width:_(s16) = G_TRUNC %2
    %sbfx:_(s16) = G_UBFX %copy, %offset, %width
    %4:_(s32) = G_ZEXT %sbfx
    $vgpr0 = COPY %4
...